| Message ID | 20180123190536.11208-12-paulo.r.zanoni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Jan 23, 2018 at 05:05:30PM -0200, Paulo Zanoni wrote: > From: Mahesh Kumar <mahesh1.kumar@intel.com> > > This patch program default values of MBus credit during pipe enable. > > Changes since V2: > - We don't need to do anything when disabling the pipe > Changes Since V1: > - Add WARN_ON (Paulo) > - Remove TODO comment > - Program 0 during pipe disable > - Rebase > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index d585ce4c8732..0dc4ef6cd46e 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5380,6 +5380,23 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, > I915_WRITE(CLKGATE_DIS_PSL(pipe), val); > } > > +static void icl_pipe_mbus_enable(struct intel_crtc *crtc) > +{ > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + enum pipe pipe = crtc->pipe; > + uint32_t val; > + > + if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0)) > + return; > + > + val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2); > + > + /* Program B credit equally to all pipes */ > + val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes); > + > + I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val); > +} > + > static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > struct drm_atomic_state *old_state) > { > @@ -5457,6 +5474,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > if (dev_priv->display.initial_watermarks != NULL) > dev_priv->display.initial_watermarks(old_intel_state, pipe_config); > > + if (INTEL_GEN(dev_priv) >= 11) > + icl_pipe_mbus_enable(intel_crtc); > + > /* XXX: Do the pipe assertions at the right place for BXT DSI. */ > if (!transcoder_is_dsi(cpu_transcoder)) > intel_enable_pipe(pipe_config); > -- > 2.14.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d585ce4c8732..0dc4ef6cd46e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5380,6 +5380,23 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, I915_WRITE(CLKGATE_DIS_PSL(pipe), val); } +static void icl_pipe_mbus_enable(struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + uint32_t val; + + if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0)) + return; + + val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2); + + /* Program B credit equally to all pipes */ + val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes); + + I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val); +} + static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, struct drm_atomic_state *old_state) { @@ -5457,6 +5474,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, if (dev_priv->display.initial_watermarks != NULL) dev_priv->display.initial_watermarks(old_intel_state, pipe_config); + if (INTEL_GEN(dev_priv) >= 11) + icl_pipe_mbus_enable(intel_crtc); + /* XXX: Do the pipe assertions at the right place for BXT DSI. */ if (!transcoder_is_dsi(cpu_transcoder)) intel_enable_pipe(pipe_config);