| Message ID | 20180123190536.11208-13-paulo.r.zanoni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Jan 23, 2018 at 05:05:31PM -0200, Paulo Zanoni wrote: > From: Mahesh Kumar <mahesh1.kumar@intel.com> > > This patch adds support to start tracking status of DBUF slices. > This is foundation to introduce support for enabling/disabling second > DBUF slice dynamically for ICL. > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_display.c | 5 +++++ > drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++++++++++++ > drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++++ > 4 files changed, 30 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index cc5ac327f267..eae18661eaec 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1435,6 +1435,7 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, > struct skl_ddb_allocation { > struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ > struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; > + uint8_t enabled_slices; /* GEN11 has configurable 2 slices */ > }; > > struct skl_wm_values { > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 0dc4ef6cd46e..bad3b112ac3e 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -11302,6 +11302,11 @@ static void verify_wm_state(struct drm_crtc *crtc, > skl_ddb_get_hw_state(dev_priv, &hw_ddb); > sw_ddb = &dev_priv->wm.skl_hw.ddb; > > + if (INTEL_GEN(dev_priv) >= 11) > + if (hw_ddb.enabled_slices != sw_ddb->enabled_slices) > + DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n", > + sw_ddb->enabled_slices, > + hw_ddb.enabled_slices); > /* planes */ > for_each_universal_plane(dev_priv, pipe, plane) { > hw_plane_wm = &hw_wm.planes[plane]; > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 0237362ccf83..e8d98857c208 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3570,6 +3570,23 @@ bool ilk_disable_lp_wm(struct drm_device *dev) > return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); > } > > +static uint8_t intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv) > +{ > + uint8_t enabled_slices; > + > + /* Slice 1 will always be enabled */ > + enabled_slices = 1; > + > + /* Gen prior to GEN11 have only one DBuf slice */ > + if (INTEL_GEN(dev_priv) < 11) > + return enabled_slices; > + > + if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE) > + enabled_slices++; > + > + return enabled_slices; > +} > + > /* > * FIXME: We still don't have the proper code detect if we need to apply the WA, > * so assume we'll always need it in order to avoid underruns. > @@ -3828,6 +3845,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, > > memset(ddb, 0, sizeof(*ddb)); > > + ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv); > + > for_each_intel_crtc(&dev_priv->drm, crtc) { > enum intel_display_power_domain power_domain; > enum plane_id plane_id; > @@ -5049,6 +5068,7 @@ skl_copy_wm_for_pipe(struct skl_wm_values *dst, > sizeof(dst->ddb.y_plane[pipe])); > memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe], > sizeof(dst->ddb.plane[pipe])); > + dst->ddb.enabled_slices = src->ddb.enabled_slices; > } > > static void > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index a6ed01a528bd..13c8dad95b84 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -2625,6 +2625,8 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv) > if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) || > !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)) > DRM_ERROR("DBuf power enable timeout\n"); > + else > + dev_priv->wm.skl_hw.ddb.enabled_slices = 2; > } > > static void icl_dbuf_disable(struct drm_i915_private *dev_priv) > @@ -2638,6 +2640,8 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv) > if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) || > (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)) > DRM_ERROR("DBuf power disable timeout!\n"); > + else > + dev_priv->wm.skl_hw.ddb.enabled_slices = 0; > } > > static void icl_mbus_init(struct drm_i915_private *dev_priv) > -- > 2.14.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index cc5ac327f267..eae18661eaec 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1435,6 +1435,7 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, struct skl_ddb_allocation { struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; + uint8_t enabled_slices; /* GEN11 has configurable 2 slices */ }; struct skl_wm_values { diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0dc4ef6cd46e..bad3b112ac3e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11302,6 +11302,11 @@ static void verify_wm_state(struct drm_crtc *crtc, skl_ddb_get_hw_state(dev_priv, &hw_ddb); sw_ddb = &dev_priv->wm.skl_hw.ddb; + if (INTEL_GEN(dev_priv) >= 11) + if (hw_ddb.enabled_slices != sw_ddb->enabled_slices) + DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n", + sw_ddb->enabled_slices, + hw_ddb.enabled_slices); /* planes */ for_each_universal_plane(dev_priv, pipe, plane) { hw_plane_wm = &hw_wm.planes[plane]; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0237362ccf83..e8d98857c208 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3570,6 +3570,23 @@ bool ilk_disable_lp_wm(struct drm_device *dev) return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); } +static uint8_t intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv) +{ + uint8_t enabled_slices; + + /* Slice 1 will always be enabled */ + enabled_slices = 1; + + /* Gen prior to GEN11 have only one DBuf slice */ + if (INTEL_GEN(dev_priv) < 11) + return enabled_slices; + + if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE) + enabled_slices++; + + return enabled_slices; +} + /* * FIXME: We still don't have the proper code detect if we need to apply the WA, * so assume we'll always need it in order to avoid underruns. @@ -3828,6 +3845,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, memset(ddb, 0, sizeof(*ddb)); + ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv); + for_each_intel_crtc(&dev_priv->drm, crtc) { enum intel_display_power_domain power_domain; enum plane_id plane_id; @@ -5049,6 +5068,7 @@ skl_copy_wm_for_pipe(struct skl_wm_values *dst, sizeof(dst->ddb.y_plane[pipe])); memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe], sizeof(dst->ddb.plane[pipe])); + dst->ddb.enabled_slices = src->ddb.enabled_slices; } static void diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index a6ed01a528bd..13c8dad95b84 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -2625,6 +2625,8 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv) if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) || !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)) DRM_ERROR("DBuf power enable timeout\n"); + else + dev_priv->wm.skl_hw.ddb.enabled_slices = 2; } static void icl_dbuf_disable(struct drm_i915_private *dev_priv) @@ -2638,6 +2640,8 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv) if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) || (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)) DRM_ERROR("DBuf power disable timeout!\n"); + else + dev_priv->wm.skl_hw.ddb.enabled_slices = 0; } static void icl_mbus_init(struct drm_i915_private *dev_priv)