| Message ID | 20180123190536.11208-8-paulo.r.zanoni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Jan 23, 2018 at 05:05:26PM -0200, Paulo Zanoni wrote: > From: Mahesh Kumar <mahesh1.kumar@intel.com> > > ICL require DDB allocation of plane to be more than "minimum display > buffer needed" for each level in order to enable WM level. > > This patch implements and consider the same while allocating DDB > and enabling WM. > > Changes Since V1: > - rebase > Changes Since V2: > - Remove extra parentheses > - Use FP16.16 only when absolutely necessary (Paulo) > Changes Since V3: > - Rebase > Changes since v4 (from Paulo) > - Coding style issue. > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 30 +++++++++++++++++++++++++++++- > 1 file changed, 29 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 44d952a3d9a6..c6d31a5075ad 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4510,6 +4510,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, > struct intel_atomic_state *state = > to_intel_atomic_state(cstate->base.state); > bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state); > + uint32_t min_disp_buf_needed; > > if (latency == 0 || > !intel_wm_plane_visible(cstate, intel_pstate)) { > @@ -4568,7 +4569,34 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, > } > } > > - if (res_blocks >= ddb_allocation || res_lines > 31) { > + if (INTEL_GEN(dev_priv) >= 11) { > + if (wp->y_tiled) { > + uint32_t extra_lines; > + uint_fixed_16_16_t fp_min_disp_buf_needed; > + > + if (res_lines % wp->y_min_scanlines == 0) > + extra_lines = wp->y_min_scanlines; > + else > + extra_lines = wp->y_min_scanlines * 2 - > + res_lines % wp->y_min_scanlines; > + > + fp_min_disp_buf_needed = mul_u32_fixed16(res_lines + > + extra_lines, > + wp->plane_blocks_per_line); > + min_disp_buf_needed = fixed16_to_u32_round_up( > + fp_min_disp_buf_needed); > + } else { > + min_disp_buf_needed = DIV_ROUND_UP(res_blocks * 11, 10); > + } > + } else { > + /* > + * To enable a WM level ddb_allocation should be > + * greater than result blocks for GEN-9/10. > + */ > + min_disp_buf_needed = res_blocks + 1; > + } > + > + if (min_disp_buf_needed > ddb_allocation || res_lines > 31) { > *enabled = false; > > /* > -- > 2.14.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Em Sex, 2018-01-26 às 15:50 -0800, James Ausmus escreveu: > On Tue, Jan 23, 2018 at 05:05:26PM -0200, Paulo Zanoni wrote: > > From: Mahesh Kumar <mahesh1.kumar@intel.com> > > > > ICL require DDB allocation of plane to be more than "minimum > > display > > buffer needed" for each level in order to enable WM level. > > > > This patch implements and consider the same while allocating DDB > > and enabling WM. > > > > Changes Since V1: > > - rebase > > Changes Since V2: > > - Remove extra parentheses > > - Use FP16.16 only when absolutely necessary (Paulo) > > Changes Since V3: > > - Rebase > > Changes since v4 (from Paulo) > > - Coding style issue. > > > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Reviewed-by: James Ausmus <james.ausmus@intel.com> > > > --- > > drivers/gpu/drm/i915/intel_pm.c | 30 > > +++++++++++++++++++++++++++++- > > 1 file changed, 29 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > b/drivers/gpu/drm/i915/intel_pm.c > > index 44d952a3d9a6..c6d31a5075ad 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -4510,6 +4510,7 @@ static int skl_compute_plane_wm(const struct > > drm_i915_private *dev_priv, > > struct intel_atomic_state *state = > > to_intel_atomic_state(cstate->base.state); > > bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state); > > + uint32_t min_disp_buf_needed; > > > > if (latency == 0 || > > !intel_wm_plane_visible(cstate, intel_pstate)) { > > @@ -4568,7 +4569,34 @@ static int skl_compute_plane_wm(const struct > > drm_i915_private *dev_priv, > > } > > } > > > > - if (res_blocks >= ddb_allocation || res_lines > 31) { > > + if (INTEL_GEN(dev_priv) >= 11) { > > + if (wp->y_tiled) { > > + uint32_t extra_lines; > > + uint_fixed_16_16_t fp_min_disp_buf_needed; > > + > > + if (res_lines % wp->y_min_scanlines == 0) > > + extra_lines = wp->y_min_scanlines; > > + else > > + extra_lines = wp->y_min_scanlines > > * 2 - > > + res_lines % wp- > > >y_min_scanlines; > > + > > + fp_min_disp_buf_needed = > > mul_u32_fixed16(res_lines + > > + extra_lines, > > + wp- > > >plane_blocks_per_line); > > + min_disp_buf_needed = > > fixed16_to_u32_round_up( > > + fp_min_disp_buf_ne > > eded); > > + } else { > > + min_disp_buf_needed = > > DIV_ROUND_UP(res_blocks * 11, 10); > > + } > > + } else { > > + /* > > + * To enable a WM level ddb_allocation should be > > + * greater than result blocks for GEN-9/10. > > + */ > > + min_disp_buf_needed = res_blocks + 1; > > + } > > + > > + if (min_disp_buf_needed > ddb_allocation || res_lines > BSpec says that if min_disp_buf_needed == ddb_allocation we should also fail, as weird as it sounds. > > 31) { > > *enabled = false; > > > > /* > > -- > > 2.14.3 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 44d952a3d9a6..c6d31a5075ad 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4510,6 +4510,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, struct intel_atomic_state *state = to_intel_atomic_state(cstate->base.state); bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state); + uint32_t min_disp_buf_needed; if (latency == 0 || !intel_wm_plane_visible(cstate, intel_pstate)) { @@ -4568,7 +4569,34 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, } } - if (res_blocks >= ddb_allocation || res_lines > 31) { + if (INTEL_GEN(dev_priv) >= 11) { + if (wp->y_tiled) { + uint32_t extra_lines; + uint_fixed_16_16_t fp_min_disp_buf_needed; + + if (res_lines % wp->y_min_scanlines == 0) + extra_lines = wp->y_min_scanlines; + else + extra_lines = wp->y_min_scanlines * 2 - + res_lines % wp->y_min_scanlines; + + fp_min_disp_buf_needed = mul_u32_fixed16(res_lines + + extra_lines, + wp->plane_blocks_per_line); + min_disp_buf_needed = fixed16_to_u32_round_up( + fp_min_disp_buf_needed); + } else { + min_disp_buf_needed = DIV_ROUND_UP(res_blocks * 11, 10); + } + } else { + /* + * To enable a WM level ddb_allocation should be + * greater than result blocks for GEN-9/10. + */ + min_disp_buf_needed = res_blocks + 1; + } + + if (min_disp_buf_needed > ddb_allocation || res_lines > 31) { *enabled = false; /*