| Message ID | 20180130092155.30419-1-mahesh1.kumar@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, 2018-01-30 at 14:51 +0530, Mahesh Kumar wrote: > From: "Kumar, Mahesh" <mahesh1.kumar@intel.com> > > Platforms before Gen11 were sharing lanes between port-A & port-E. > This limitation is no more there. > > Changes since V1: > - optimize the code (Shashank/Jani) > - create helper function to get max lanes (ville) > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > --- > drivers/gpu/drm/i915/intel_ddi.c | 43 +++++++++++++++++----------------------- > 1 file changed, 18 insertions(+), 25 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index e51559be2e3b..4bde742a8ff4 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -2842,6 +2842,23 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) > return false; > } > > +static int > +intel_ddi_max_lanes(struct drm_i915_private *dev_priv, enum port port) > +{ > + if (INTEL_GEN(dev_priv) >= 11) > + return 4; > + > + if (port == PORT_A || port == PORT_E) { > + if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) Is the expectation that bios has already written the correct value depending on the board? The patch itself looks correct Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > + return port == PORT_A ? 4 : 0; > + else > + /* Both A and E share 2 lanes */ > + return 2; > + } > + > + return 4; > +} > + > void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > { > struct intel_digital_port *intel_dig_port; > @@ -2850,31 +2867,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > bool init_hdmi, init_dp, init_lspcon = false; > int max_lanes; > > - if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) { > - switch (port) { > - case PORT_A: > - max_lanes = 4; > - break; > - case PORT_E: > - max_lanes = 0; > - break; > - default: > - max_lanes = 4; > - break; > - } > - } else { > - switch (port) { > - case PORT_A: > - max_lanes = 2; > - break; > - case PORT_E: > - max_lanes = 2; > - break; > - default: > - max_lanes = 4; > - break; > - } > - } > + max_lanes = intel_ddi_max_lanes(dev_priv, port); > > init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || > dev_priv->vbt.ddi_port_info[port].supports_hdmi);
On Tue, Jan 30, 2018 at 07:52:14PM +0000, Pandiyan, Dhinakaran wrote: > > On Tue, 2018-01-30 at 14:51 +0530, Mahesh Kumar wrote: > > From: "Kumar, Mahesh" <mahesh1.kumar@intel.com> > > > > Platforms before Gen11 were sharing lanes between port-A & port-E. > > This limitation is no more there. > > > > Changes since V1: > > - optimize the code (Shashank/Jani) > > - create helper function to get max lanes (ville) > > > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > > --- > > drivers/gpu/drm/i915/intel_ddi.c | 43 +++++++++++++++++----------------------- > > 1 file changed, 18 insertions(+), 25 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > > index e51559be2e3b..4bde742a8ff4 100644 > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > @@ -2842,6 +2842,23 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) > > return false; > > } > > > > +static int > > +intel_ddi_max_lanes(struct drm_i915_private *dev_priv, enum port port) > > +{ > > + if (INTEL_GEN(dev_priv) >= 11) > > + return 4; > > + > > + if (port == PORT_A || port == PORT_E) { > > + if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) > > > Is the expectation that bios has already written the correct value > depending on the board? We have a fixup later on for BIOS fails. Might be nice to try and pull that in as well so that we would have all the logic in one clear place. > > The patch itself looks correct > Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > > > > + return port == PORT_A ? 4 : 0; > > + else > > + /* Both A and E share 2 lanes */ > > + return 2; > > + } > > + > > + return 4; > > +} > > + > > void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > > { > > struct intel_digital_port *intel_dig_port; > > @@ -2850,31 +2867,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > > bool init_hdmi, init_dp, init_lspcon = false; > > int max_lanes; > > > > - if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) { > > - switch (port) { > > - case PORT_A: > > - max_lanes = 4; > > - break; > > - case PORT_E: > > - max_lanes = 0; > > - break; > > - default: > > - max_lanes = 4; > > - break; > > - } > > - } else { > > - switch (port) { > > - case PORT_A: > > - max_lanes = 2; > > - break; > > - case PORT_E: > > - max_lanes = 2; > > - break; > > - default: > > - max_lanes = 4; > > - break; > > - } > > - } > > + max_lanes = intel_ddi_max_lanes(dev_priv, port); > > > > init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || > > dev_priv->vbt.ddi_port_info[port].supports_hdmi); > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index e51559be2e3b..4bde742a8ff4 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2842,6 +2842,23 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) return false; } +static int +intel_ddi_max_lanes(struct drm_i915_private *dev_priv, enum port port) +{ + if (INTEL_GEN(dev_priv) >= 11) + return 4; + + if (port == PORT_A || port == PORT_E) { + if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) + return port == PORT_A ? 4 : 0; + else + /* Both A and E share 2 lanes */ + return 2; + } + + return 4; +} + void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) { struct intel_digital_port *intel_dig_port; @@ -2850,31 +2867,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) bool init_hdmi, init_dp, init_lspcon = false; int max_lanes; - if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) { - switch (port) { - case PORT_A: - max_lanes = 4; - break; - case PORT_E: - max_lanes = 0; - break; - default: - max_lanes = 4; - break; - } - } else { - switch (port) { - case PORT_A: - max_lanes = 2; - break; - case PORT_E: - max_lanes = 2; - break; - default: - max_lanes = 4; - break; - } - } + max_lanes = intel_ddi_max_lanes(dev_priv, port); init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || dev_priv->vbt.ddi_port_info[port].supports_hdmi);