| Message ID | 20180216145754.14428-6-a.hajda@samsung.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
On 2018년 02월 16일 23:57, Andrzej Hajda wrote: > Rates declared in PLL rate tables should match exactly rates calculated > from PLL coefficients. If that is not the case, rate of parent might be being > set not as expected. For instance, if in the PLL rates table we have > a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate > callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate > will return 393216003. If we now attempt to set rate of a PLL's child divider > clock to 393216000/2 its rate will be 131072001, rather than 196608000. > That is the divider will be set to 3 instead of 2, because 393216003/2 is > greater than 196608000. > > To fix this issue declared rates are changed to exactly match rates generated > by a PLL, as calculated from the P, M, S, K coefficients. > > Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> > Acked-by: Tomasz Figa <tomasz.figa@gmail.com> > --- > drivers/clk/samsung/clk-exynos7.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c > index 5931a4140c3d..bbfa57b4e017 100644 > --- a/drivers/clk/samsung/clk-exynos7.c > +++ b/drivers/clk/samsung/clk-exynos7.c > @@ -140,7 +140,7 @@ static const struct samsung_div_clock topc_div_clks[] __initconst = { > }; > > static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = { > - PLL_36XX_RATE(491520000, 20, 1, 0, 31457), > + PLL_36XX_RATE(491519897, 20, 1, 0, 31457), > {}, > }; > > Looks good to me. Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 5931a4140c3d..bbfa57b4e017 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -140,7 +140,7 @@ static const struct samsung_div_clock topc_div_clks[] __initconst = { }; static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = { - PLL_36XX_RATE(491520000, 20, 1, 0, 31457), + PLL_36XX_RATE(491519897, 20, 1, 0, 31457), {}, };