| Message ID | 20180223123555.64009-7-icenowy@aosc.io (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Feb 23, 2018 at 08:35:54PM +0800, Icenowy Zheng wrote: > Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its > memory map fully reworked and some high-speed peripherals (PCIe, USB > 3.0) introduced. > > This commit adds the basical DTSI file of it, including the clock > support and UART support. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > Reviewed-by: Andre Przywara <andre.przywara@arm.com> > --- > Changes in v3: > - SPDX license identifier fix. > > Changes in v2: > - Add APB1 clock as PIO's APB clock. > - Switched to SPDX license identifier. > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 177 +++++++++++++++++++++++++++ > 1 file changed, 177 insertions(+) > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > new file mode 100644 > index 000000000000..4a6236bd9778 > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > @@ -0,0 +1,177 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/sun50i-h6-ccu.h> > +#include <dt-bindings/reset/sun50i-h6-ccu.h> > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@1 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <1>; > + enable-method = "psci"; > + }; > + > + cpu2: cpu@2 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <2>; > + enable-method = "psci"; > + }; > + > + cpu3: cpu@3 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <3>; > + enable-method = "psci"; > + }; > + }; > + > + iosc: internal-osc-clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <16000000>; > + clock-accuracy = <300000000>; > + clock-output-names = "iosc"; > + }; You're not using it anywhere > + osc24M: osc24M_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "osc24M"; > + }; > + > + osc32k: osc32k_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + clock-output-names = "osc32k"; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; Is it needed? The bootloader should fill it with whatever version it has, shouldn't it? Thanks! Maxime
于 2018年2月23日 GMT+08:00 下午11:20:38, Maxime Ripard <maxime.ripard@bootlin.com> 写到: >On Fri, Feb 23, 2018 at 08:35:54PM +0800, Icenowy Zheng wrote: >> Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with >its >> memory map fully reworked and some high-speed peripherals (PCIe, USB >> 3.0) introduced. >> >> This commit adds the basical DTSI file of it, including the clock >> support and UART support. >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> Reviewed-by: Andre Przywara <andre.przywara@arm.com> >> --- >> Changes in v3: >> - SPDX license identifier fix. >> >> Changes in v2: >> - Add APB1 clock as PIO's APB clock. >> - Switched to SPDX license identifier. >> >> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 177 >+++++++++++++++++++++++++++ >> 1 file changed, 177 insertions(+) >> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >> >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >> new file mode 100644 >> index 000000000000..4a6236bd9778 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >> @@ -0,0 +1,177 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ or MIT) >> +/* >> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> >> + */ >> + >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/clock/sun50i-h6-ccu.h> >> +#include <dt-bindings/reset/sun50i-h6-ccu.h> >> + >> +/ { >> + interrupt-parent = <&gic>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu0: cpu@0 { >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + device_type = "cpu"; >> + reg = <0>; >> + enable-method = "psci"; >> + }; >> + >> + cpu1: cpu@1 { >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + device_type = "cpu"; >> + reg = <1>; >> + enable-method = "psci"; >> + }; >> + >> + cpu2: cpu@2 { >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + device_type = "cpu"; >> + reg = <2>; >> + enable-method = "psci"; >> + }; >> + >> + cpu3: cpu@3 { >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + device_type = "cpu"; >> + reg = <3>; >> + enable-method = "psci"; >> + }; >> + }; >> + >> + iosc: internal-osc-clk { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + clock-frequency = <16000000>; >> + clock-accuracy = <300000000>; >> + clock-output-names = "iosc"; >> + }; > >You're not using it anywhere > >> + osc24M: osc24M_clk { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + clock-frequency = <24000000>; >> + clock-output-names = "osc24M"; >> + }; >> + >> + osc32k: osc32k_clk { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + clock-frequency = <32768>; >> + clock-output-names = "osc32k"; >> + }; >> + >> + psci { >> + compatible = "arm,psci-0.2"; >> + method = "smc"; >> + }; > >Is it needed? The bootloader should fill it with whatever version it >has, shouldn't it? But we now use ATF rather than U-Boot PSCI. U-Boot will not fill ATF info. See A64/H5 device trees. > >Thanks! >Maxime
On Fri, Feb 23, 2018 at 11:22:06PM +0800, Icenowy Zheng wrote: > >> + psci { > >> + compatible = "arm,psci-0.2"; > >> + method = "smc"; > >> + }; > > > >Is it needed? The bootloader should fill it with whatever version it > >has, shouldn't it? > > But we now use ATF rather than U-Boot PSCI. U-Boot will not fill ATF > info. > > See A64/H5 device trees. So if the PSCI version implemented in ATF ever changes, we would have to update all the DT everywhere, but only if you're running the new version? Sigh. Maxime
On 02/26/18 03:26, Maxime Ripard wrote: > On Fri, Feb 23, 2018 at 11:22:06PM +0800, Icenowy Zheng wrote: >>>> + psci { >>>> + compatible = "arm,psci-0.2"; >>>> + method = "smc"; >>>> + }; >>> >>> Is it needed? The bootloader should fill it with whatever version it >>> has, shouldn't it? >> >> But we now use ATF rather than U-Boot PSCI. U-Boot will not fill ATF >> info. >> >> See A64/H5 device trees. > > So if the PSCI version implemented in ATF ever changes, we would have > to update all the DT everywhere, but only if you're running the new > version? Yes but no. PSCI 1.0 is generally backward compatible with PSCI 0.2. In fact, the Linux driver treats them exactly the same: { .compatible = "arm,psci-0.2", .data = psci_0_2_init}, { .compatible = "arm,psci-1.0", .data = psci_0_2_init}, For the H6, however, the oldest ATF source available (which I believe was the one in use during bringup) is based on mainline 1.4, and is already at PSCI version 1.1: [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.1 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. So we could go ahead and bump the compatible to "arm,psci-1.0". Thanks, Samuel
Hi, On 26/02/18 15:54, Samuel Holland wrote: > On 02/26/18 03:26, Maxime Ripard wrote: >> On Fri, Feb 23, 2018 at 11:22:06PM +0800, Icenowy Zheng wrote: >>>>> + psci { >>>>> + compatible = "arm,psci-0.2"; >>>>> + method = "smc"; >>>>> + }; >>>> >>>> Is it needed? The bootloader should fill it with whatever version it >>>> has, shouldn't it? >>> >>> But we now use ATF rather than U-Boot PSCI. U-Boot will not fill ATF >>> info. >>> >>> See A64/H5 device trees. >> >> So if the PSCI version implemented in ATF ever changes, we would have >> to update all the DT everywhere, but only if you're running the new >> version? > > Yes but no. PSCI 1.0 is generally backward compatible with PSCI 0.2. In fact, > the Linux driver treats them exactly the same: > > { .compatible = "arm,psci-0.2", .data = psci_0_2_init}, > { .compatible = "arm,psci-1.0", .data = psci_0_2_init}, Yeah, it's actually unclear why we have that new compatible name in the first place, since starting with PSCI v0.2 the version can be perfectly read using the mandatory PSCI_VERSION call. And DT aims to only cover things that are not discoverable. > For the H6, however, the oldest ATF source available (which I believe was the > one in use during bringup) is based on mainline 1.4, and is already at PSCI > version 1.1: > > [ 0.000000] psci: probing for conduit method from DT. > [ 0.000000] psci: PSCIv1.1 detected in firmware. > [ 0.000000] psci: Using standard PSCI v0.2 function IDs > [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. > > So we could go ahead and bump the compatible to "arm,psci-1.0". I'd rather leave it at "arm,psci-0.2", since this improves compatibility to other OSes or DT users. Cheers, Andre.
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi new file mode 100644 index 000000000000..4a6236bd9778 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun50i-h6-ccu.h> +#include <dt-bindings/reset/sun50i-h6-ccu.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; + }; + }; + + iosc: internal-osc-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-accuracy = <300000000>; + clock-output-names = "iosc"; + }; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ccu: clock@3001000 { + compatible = "allwinner,sun50i-h6-ccu"; + reg = <0x03001000 0x1000>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gic: interrupt-controller@3021000 { + compatible = "arm,gic-400"; + reg = <0x03021000 0x1000>, + <0x03022000 0x2000>, + <0x03024000 0x2000>, + <0x03026000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + pio: pinctrl@300b000 { + compatible = "allwinner,sun50i-h6-pinctrl"; + reg = <0x0300b000 0x400>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + uart0_ph_pins: uart0-ph { + pins = "PH0", "PH1"; + function = "uart0"; + }; + }; + + uart0: serial@5000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000000 0x400>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@5000400 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000400 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@5000800 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000800 0x400>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@5000c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000c00 0x400>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + }; +};