| Message ID | 20180224214545.3740-2-jernej.skrabec@siol.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi, On Sat, Feb 24, 2018 at 10:45:31PM +0100, Jernej Skrabec wrote: > Some NM PLLs doesn't work well when their output clock rate is set below > certain rate. > > Add support for that constrain. In such a case, you should round the rate to the minimum the clock can operate at, and not return an error. Thanks! Maxime
On Mon, Feb 26, 2018 at 5:38 PM, Maxime Ripard <maxime.ripard@bootlin.com> wrote: > Hi, > > On Sat, Feb 24, 2018 at 10:45:31PM +0100, Jernej Skrabec wrote: >> Some NM PLLs doesn't work well when their output clock rate is set below >> certain rate. >> >> Add support for that constrain. > > In such a case, you should round the rate to the minimum the clock can > operate at, and not return an error. That's true for round_rate. But what's the expected behavior of set_rate? AFAIK we presume all users call round_rate before set_rate, but that doesn't seem to be true all the time. ChenYu
On Mon, Feb 26, 2018 at 05:43:01PM +0800, Chen-Yu Tsai wrote: > On Mon, Feb 26, 2018 at 5:38 PM, Maxime Ripard > <maxime.ripard@bootlin.com> wrote: > > Hi, > > > > On Sat, Feb 24, 2018 at 10:45:31PM +0100, Jernej Skrabec wrote: > >> Some NM PLLs doesn't work well when their output clock rate is set below > >> certain rate. > >> > >> Add support for that constrain. > > > > In such a case, you should round the rate to the minimum the clock can > > operate at, and not return an error. > > That's true for round_rate. But what's the expected behavior of set_rate? > AFAIK we presume all users call round_rate before set_rate, but that doesn't > seem to be true all the time. One of the first things that happens during a set_rate is a round_rate: https://elixir.bootlin.com/linux/v4.16-rc3/source/drivers/clk/clk.c#L1873 Maxime
On Mon, Feb 26, 2018 at 6:25 PM, Maxime Ripard <maxime.ripard@bootlin.com> wrote: > On Mon, Feb 26, 2018 at 05:43:01PM +0800, Chen-Yu Tsai wrote: >> On Mon, Feb 26, 2018 at 5:38 PM, Maxime Ripard >> <maxime.ripard@bootlin.com> wrote: >> > Hi, >> > >> > On Sat, Feb 24, 2018 at 10:45:31PM +0100, Jernej Skrabec wrote: >> >> Some NM PLLs doesn't work well when their output clock rate is set below >> >> certain rate. >> >> >> >> Add support for that constrain. >> > >> > In such a case, you should round the rate to the minimum the clock can >> > operate at, and not return an error. >> >> That's true for round_rate. But what's the expected behavior of set_rate? >> AFAIK we presume all users call round_rate before set_rate, but that doesn't >> seem to be true all the time. > > One of the first things that happens during a set_rate is a round_rate: > https://elixir.bootlin.com/linux/v4.16-rc3/source/drivers/clk/clk.c#L1873 Ah! This was added recently in commit ca5e089a32c5 ("clk: use round rate to bail out early in set_rate"). Thanks for the tip! ChenYu
Hi, Dne ponedeljek, 26. februar 2018 ob 10:38:00 CET je Maxime Ripard napisal(a): > Hi, > > On Sat, Feb 24, 2018 at 10:45:31PM +0100, Jernej Skrabec wrote: > > Some NM PLLs doesn't work well when their output clock rate is set below > > certain rate. > > > > Add support for that constrain. > > In such a case, you should round the rate to the minimum the clock can > operate at, and not return an error. OK. Best regards, Jernej
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c index a16de092bf94..c5ca62a9c2b9 100644 --- a/drivers/clk/sunxi-ng/ccu_nm.c +++ b/drivers/clk/sunxi-ng/ccu_nm.c @@ -20,7 +20,7 @@ struct _ccu_nm { }; static void ccu_nm_find_best(unsigned long parent, unsigned long rate, - struct _ccu_nm *nm) + unsigned long min_rate, struct _ccu_nm *nm) { unsigned long best_rate = 0; unsigned long best_n = 0, best_m = 0; @@ -30,7 +30,7 @@ static void ccu_nm_find_best(unsigned long parent, unsigned long rate, for (_m = nm->min_m; _m <= nm->max_m; _m++) { unsigned long tmp_rate = parent * _n / _m; - if (tmp_rate > rate) + if (tmp_rate > rate || tmp_rate < min_rate) continue; if ((rate - tmp_rate) < (rate - best_rate)) { @@ -134,7 +134,7 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate, _nm.min_m = 1; _nm.max_m = nm->m.max ?: 1 << nm->m.width; - ccu_nm_find_best(*parent_rate, rate, &_nm); + ccu_nm_find_best(*parent_rate, rate, nm->min_rate, &_nm); rate = *parent_rate * _nm.n / _nm.m; if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) @@ -155,6 +155,9 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate, if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) rate = rate * nm->fixed_post_div; + if (rate < nm->min_rate) + return -EINVAL; + if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) { spin_lock_irqsave(nm->common.lock, flags); @@ -186,7 +189,7 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate, &_nm.m, &_nm.n); } else { ccu_sdm_helper_disable(&nm->common, &nm->sdm); - ccu_nm_find_best(parent_rate, rate, &_nm); + ccu_nm_find_best(parent_rate, rate, nm->min_rate, &_nm); } spin_lock_irqsave(nm->common.lock, flags); diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h index eba586b4c7d0..1d8b459c50b7 100644 --- a/drivers/clk/sunxi-ng/ccu_nm.h +++ b/drivers/clk/sunxi-ng/ccu_nm.h @@ -37,6 +37,7 @@ struct ccu_nm { struct ccu_sdm_internal sdm; unsigned int fixed_post_div; + unsigned int min_rate; struct ccu_common common; }; @@ -88,6 +89,32 @@ struct ccu_nm { }, \ } +#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(_struct, _name, _parent, \ + _reg, _min_rate, \ + _nshift, _nwidth, \ + _mshift, _mwidth, \ + _frac_en, _frac_sel, \ + _frac_rate_0, _frac_rate_1,\ + _gate, _lock, _flags) \ + struct ccu_nm _struct = { \ + .enable = _gate, \ + .lock = _lock, \ + .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \ + .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ + .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \ + _frac_rate_0, \ + _frac_rate_1), \ + .min_rate = _min_rate, \ + .common = { \ + .reg = _reg, \ + .features = CCU_FEATURE_FRACTIONAL, \ + .hw.init = CLK_HW_INIT(_name, \ + _parent, \ + &ccu_nm_ops, \ + _flags), \ + }, \ + } + #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ _nshift, _nwidth, \ _mshift, _mwidth, \
Some NM PLLs doesn't work well when their output clock rate is set below certain rate. Add support for that constrain. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> --- drivers/clk/sunxi-ng/ccu_nm.c | 11 +++++++---- drivers/clk/sunxi-ng/ccu_nm.h | 27 +++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 4 deletions(-)