| Message ID | 1520253911-46218-1-git-send-email-d.schultz@phytec.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Daniel, Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz: > The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. > Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. > > Signed-off-by: Daniel Schultz <d.schultz@phytec.de> > --- > > The binding will be added with the next merge of net-next: > https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/commit/?id=9708fb630d19ee51ae3aeb3a533e3010da0e8570 I did find the commit, but no related change of the dp83867 dt binding document [0], including a review by dt-maintainers. While your property does not look overly complicated, the binding should be updated nontheless. Heiko [0] https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/log/Documentation/devicetree/bindings/net/ti,dp83867.txt?id=9708fb630d19ee51ae3aeb3a533e3010da0e8570 > arch/arm/boot/dts/rk3288-phycore-som.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi > index bdd80aa..e60535d 100644 > --- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi > +++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi > @@ -141,6 +141,7 @@ > ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; > ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > enet-phy-lane-no-swap; > + ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>; > }; > }; > }; >
Hi, On 03/05/2018 03:15 PM, Heiko Stuebner wrote: > Hi Daniel, > > Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz: >> The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. >> Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. >> >> Signed-off-by: Daniel Schultz <d.schultz@phytec.de> >> --- >> >> The binding will be added with the next merge of net-next: >> https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/commit/?id=9708fb630d19ee51ae3aeb3a533e3010da0e8570 https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/log/Documentation/devicetree/bindings/net/ti,dp83867.txt If I search in the master branch, I get the patch. Did I searched wrong? Daniel > I did find the commit, but no related change of the dp83867 dt binding > document [0], including a review by dt-maintainers. > > While your property does not look overly complicated, the binding > should be updated nontheless. > > > Heiko > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/log/Documentation/devicetree/bindings/net/ti,dp83867.txt?id=9708fb630d19ee51ae3aeb3a533e3010da0e8570 > >> arch/arm/boot/dts/rk3288-phycore-som.dtsi | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi >> index bdd80aa..e60535d 100644 >> --- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi >> +++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi >> @@ -141,6 +141,7 @@ >> ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; >> ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; >> enet-phy-lane-no-swap; >> + ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>; >> }; >> }; >> }; >> >
Hi Daniel, Am Montag, 5. März 2018, 16:57:13 CET schrieb Daniel Schultz: > On 03/05/2018 03:15 PM, Heiko Stuebner wrote: > > Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz: > >> The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. > >> Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. > >> > >> Signed-off-by: Daniel Schultz <d.schultz@phytec.de> > >> --- > >> > >> The binding will be added with the next merge of net-next: > >> https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/commit > >> /?id=9708fb630d19ee51ae3aeb3a533e3010da0e8570 > https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/log/Docum > entation/devicetree/bindings/net/ti,dp83867.txt > > If I search in the master branch, I get the patch. Did I searched wrong? no ... seems I was just blind :-) Heiko > > I did find the commit, but no related change of the dp83867 dt binding > > document [0], including a review by dt-maintainers. > > > > While your property does not look overly complicated, the binding > > should be updated nontheless. > > > > > > Heiko > > > > [0] > > https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/log/Do > > cumentation/devicetree/bindings/net/ti,dp83867.txt?id=9708fb630d19ee51ae3a > > eb3a533e3010da0e8570> > >> arch/arm/boot/dts/rk3288-phycore-som.dtsi | 1 + > >> 1 file changed, 1 insertion(+) > >> > >> diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi > >> b/arch/arm/boot/dts/rk3288-phycore-som.dtsi index bdd80aa..e60535d > >> 100644 > >> --- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi > >> +++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi > >> @@ -141,6 +141,7 @@ > >> > >> ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; > >> ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > >> enet-phy-lane-no-swap; > >> > >> + ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>; > >> > >> }; > >> > >> }; > >> > >> };
Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz: > The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. > Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. > > Signed-off-by: Daniel Schultz <d.schultz@phytec.de> applied for 4.17 Thanks Heiko
Am Montag, 5. März 2018, 21:25:30 CET schrieb Heiko Stübner: > Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz: > > The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. > > Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. > > > > Signed-off-by: Daniel Schultz <d.schultz@phytec.de> > > applied for 4.17 had to move it to 4.18 though. The change to the dt-binding header goes through the networking tree and will only get merged for 4.17-rc1 . So devicetree changes in a different branch aren't available at this point. One commonly practiced alternative is that you provide a v2 with the actual hex values instead of the constants for 4.17 and a follow-up patch replacing them with the constants that I can apply for 4.18. Heiko
Hi, On 03/05/2018 10:08 PM, Heiko Stübner wrote: > Am Montag, 5. März 2018, 21:25:30 CET schrieb Heiko Stübner: >> Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz: >>> The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. >>> Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. >>> >>> Signed-off-by: Daniel Schultz <d.schultz@phytec.de> >> applied for 4.17 > had to move it to 4.18 though. > > The change to the dt-binding header goes through the networking > tree and will only get merged for 4.17-rc1 . > > So devicetree changes in a different branch aren't available at this > point. > > One commonly practiced alternative is that you provide a v2 > with the actual hex values instead of the constants for 4.17 > and a follow-up patch replacing them with the constants > that I can apply for 4.18. It's not so urgent because the RK818 PMIC currently does not boot and the patch for this problem is also pending.
diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi index bdd80aa..e60535d 100644 --- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi @@ -141,6 +141,7 @@ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; enet-phy-lane-no-swap; + ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>; }; }; };
The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> --- The binding will be added with the next merge of net-next: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/commit/?id=9708fb630d19ee51ae3aeb3a533e3010da0e8570 arch/arm/boot/dts/rk3288-phycore-som.dtsi | 1 + 1 file changed, 1 insertion(+)