diff mbox

[v8,3/5] arm64: dts: add ufs dts node

Message ID 20180213101412.5717-4-liwei213@huawei.com (mailing list archive)
State Not Applicable
Headers show

Commit Message

Wei Li Feb. 13, 2018, 10:14 a.m. UTC
arm64: dts: add ufs node for Hisilicon.

Signed-off-by: Li Wei <liwei213@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

Comments

Wei Xu March 8, 2018, 4:57 p.m. UTC | #1
Hi Li Wei,

On 2018/2/13 10:14, Li Wei wrote:
> arm64: dts: add ufs node for Hisilicon.
> 
> Signed-off-by: Li Wei <liwei213@huawei.com>

Fine to me. Thanks!

Acked-by: Wei Xu <xuwei5@hisilicon.com>

Best Regards,
Wei

> ---
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index ab0b95ba5ae5..d0dfa97fdad1 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -904,6 +904,25 @@
>  			reset-gpios = <&gpio11 1 0 >;
>  		};
>  
> +		/* UFS */
> +		ufs: ufs@ff3b0000 {
> +			compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
> +			/* 0: HCI standard */
> +			/* 1: UFS SYS CTRL */
> +			reg = <0x0 0xff3b0000 0x0 0x1000>,
> +				<0x0 0xff3b1000 0x0 0x1000>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
> +				<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
> +			clock-names = "ref_clk", "phy_clk";
> +			/* offset: 0x84; bit: 12 */
> +			/* offset: 0x84; bit: 7  */
> +			resets = <&crg_rst 0x84 12>,
> +				<&crg_rst 0x84 7>;
> +			reset-names = "rst", "assert";
> +		};
> +
>  		/* SD */
>  		dwmmc1: dwmmc1@ff37f000 {
>  			#address-cells = <1>;
>
diff mbox

Patch

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index ab0b95ba5ae5..d0dfa97fdad1 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -904,6 +904,25 @@ 
 			reset-gpios = <&gpio11 1 0 >;
 		};
 
+		/* UFS */
+		ufs: ufs@ff3b0000 {
+			compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
+			/* 0: HCI standard */
+			/* 1: UFS SYS CTRL */
+			reg = <0x0 0xff3b0000 0x0 0x1000>,
+				<0x0 0xff3b1000 0x0 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
+				<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
+			clock-names = "ref_clk", "phy_clk";
+			/* offset: 0x84; bit: 12 */
+			/* offset: 0x84; bit: 7  */
+			resets = <&crg_rst 0x84 12>,
+				<&crg_rst 0x84 7>;
+			reset-names = "rst", "assert";
+		};
+
 		/* SD */
 		dwmmc1: dwmmc1@ff37f000 {
 			#address-cells = <1>;