| Message ID | 20180316230501.974-3-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, 2018-03-16 at 16:04 -0700, José Roberto de Souza wrote: > From: "Souza, Jose" <jose.souza@intel.com> > > For Geminilake and Cannonlake+ the Y-coordinate support must be > enabled in PSR2_CTL too. > > Spec: 7713 > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > > v2: This is specific to Geminilake and Cannonlake+ > > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > drivers/gpu/drm/i915/intel_psr.c | 6 ++++-- > 2 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 1e000f3004cb..bac54f744913 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3869,6 +3869,8 @@ enum { > #define EDP_PSR2_CTL _MMIO(0x6f900) > #define EDP_PSR2_ENABLE (1<<31) > #define EDP_SU_TRACK_ENABLE (1<<30) > +#define EDP_Y_COORDINATE_VALID (1<<26) /* GLK and CNL+ */ > +#define EDP_Y_COORDINATE_ENABLE (1<<25) /* GLK and CNL+ */ > #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20) > #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20) > #define EDP_PSR2_TP2_TIME_500 (0<<8) > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index 5593d1f3049a..c5eeb13cbcfd 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -417,8 +417,10 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > /* FIXME: selective update is probably totally broken because it doesn't > * mesh at all with our frontbuffer tracking. And the hw alone isn't > * good enough. */ > - val |= EDP_PSR2_ENABLE | > - EDP_SU_TRACK_ENABLE; > + val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; > + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { > + val |= EDP_Y_COORDINATE_VALID | EDP_Y_COORDINATE_ENABLE; > + } The corresponding bits for gen-9 are set in hsw_psr_enable_source. > > if (drm_dp_dpcd_readb(&intel_dp->aux, > DP_SYNCHRONIZATION_LATENCY_IN_SINK,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1e000f3004cb..bac54f744913 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3869,6 +3869,8 @@ enum { #define EDP_PSR2_CTL _MMIO(0x6f900) #define EDP_PSR2_ENABLE (1<<31) #define EDP_SU_TRACK_ENABLE (1<<30) +#define EDP_Y_COORDINATE_VALID (1<<26) /* GLK and CNL+ */ +#define EDP_Y_COORDINATE_ENABLE (1<<25) /* GLK and CNL+ */ #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20) #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20) #define EDP_PSR2_TP2_TIME_500 (0<<8) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 5593d1f3049a..c5eeb13cbcfd 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -417,8 +417,10 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) /* FIXME: selective update is probably totally broken because it doesn't * mesh at all with our frontbuffer tracking. And the hw alone isn't * good enough. */ - val |= EDP_PSR2_ENABLE | - EDP_SU_TRACK_ENABLE; + val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { + val |= EDP_Y_COORDINATE_VALID | EDP_Y_COORDINATE_ENABLE; + } if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SYNCHRONIZATION_LATENCY_IN_SINK,