| Message ID | 1521800336-19266-6-git-send-email-sricharan@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri 23 Mar 03:18 PDT 2018, Sricharan R wrote: > + soc { > + pinctrl@1000000 { > + serial_0_pins: serial0_pinmux { Please, no underscores in the node name. > + mux { Fyi, you can put the pinctrl properties directly into the state node, omitting the "mux" level. > + pins = "gpio16", "gpio17"; > + function = "blsp_uart0"; > + bias-disable; > + }; > + }; > + Apart from this the patch looks good. Regards, Bjorn
On 3/27/2018 10:34 PM, Bjorn Andersson wrote: > On Fri 23 Mar 03:18 PDT 2018, Sricharan R wrote: >> + soc { >> + pinctrl@1000000 { >> + serial_0_pins: serial0_pinmux { > > Please, no underscores in the node name. ok. > >> + mux { > > Fyi, you can put the pinctrl properties directly into the state node, > omitting the "mux" level. > ok, will change. >> + pins = "gpio16", "gpio17"; >> + function = "blsp_uart0"; >> + bias-disable; >> + }; >> + }; >> + > > Apart from this the patch looks good. Thanks. Regards, Sricharan
On Freitag, 23. März 2018 15:48:48 CEST Sricharan R wrote: > Add the common parts for the dk04 boards. > > Reviewed-by: Abhishek Sahu <absahu@codeaurora.org> > Signed-off-by: Sricharan R <sricharan@codeaurora.org> > --- > arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 115 ++++++++++++++++++++++++++ > arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +- > 2 files changed, 116 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi The no-map reserved-memory for tz and smem are missing. Linux doesn't have control over these regions and they are placed in the middle of the ram before Linux even starts. And u-boot is also not adding these ranges automatically. reserved-memory { #address-cells = <0x1>; #size-cells = <0x1>; ranges; smem@87e00000 { reg = <0x87e00000 0x080000>; no-map; }; tz@87e80000 { reg = <0x87e80000 0x180000>; no-map; }; }; This can either (depending on HW/SW configuration) lead to a failed boot [1] or to runtime crashes like: root@OpenWrt:/# /tmp/memory-allocator-test main 0 [ 571.758058] Unhandled fault: imprecise external abort (0xc06) at 0x01715ff8 [ 571.758099] pgd = cebec000 [ 571.763826] [01715ff8] *pgd=8e7fa835, *pte=87e7f75f, *ppte=87e7fc7f Bus error I would not know how to disable QSEE on these boards and thus would assume that it should be part of this dtsi. Kind regards, Sven [1] https://www.spinics.net/lists/linux-arm-msm/msg21536.html
On Mittwoch, 18. April 2018 08:59:46 CEST Sven Eckelmann wrote: [...] > I would not know how to disable QSEE on these boards and thus would assume > that it should be part of this dtsi. Just did some reviews of the reserved-memory regions in other QCA devices and it looks like this tz and smem are often directly added to the SoC dtsi. So I will prepare a similar change for qcom-ipq4019.dtsi and this would then solve it for AP-DK01/04/07 and no changes in the board-family specific dtsi would be necessary. But maybe someone has an objection because tz and smem can actually be disabled in a sane way on these SoCs and thus it would be better to have these regions in the board specific dts(i) files. We will see... Kind regards, Sven
Hi Sven, On 4/18/2018 12:37 PM, Sven Eckelmann wrote: > On Mittwoch, 18. April 2018 08:59:46 CEST Sven Eckelmann wrote: > [...] >> I would not know how to disable QSEE on these boards and thus would assume >> that it should be part of this dtsi. > > > Just did some reviews of the reserved-memory regions in other QCA devices and > it looks like this tz and smem are often directly added to the SoC dtsi. So I > will prepare a similar change for qcom-ipq4019.dtsi and this would then solve > it for AP-DK01/04/07 and no changes in the board-family specific dtsi would be > necessary. > > But maybe someone has an objection because tz and smem can actually be > disabled in a sane way on these SoCs and thus it would be better to have these > regions in the board specific dts(i) files. We will see... Right, will add the above change to soc.dtsi in V6. Does that sound ok for you ? Regards, Sricharan
Hi, On Mittwoch, 18. April 2018 12:45:20 CEST Sricharan R wrote: > Right, will add the above change to soc.dtsi in V6. Does that sound ok for > you ? I have submitted a patch for this now [1] because I need this for OpenWrt (sooner rather than later). And I am not sure whether it is good to have this in your feature series because it is a bugfix which might even qualify for stable@vger.kernel.org. I hope this patch [1] is ok for you. Kind regards, Sven [1] https://patchwork.kernel.org/patch/10347459/
Hi Sven, On 4/18/2018 1:08 PM, Sven Eckelmann wrote: > Hi, > > On Mittwoch, 18. April 2018 12:45:20 CEST Sricharan R wrote: >> Right, will add the above change to soc.dtsi in V6. Does that sound ok for >> you ? > > I have submitted a patch for this now [1] because I need this for OpenWrt > (sooner rather than later). And I am not sure whether it is good to have this > in your feature series because it is a bugfix which might even qualify for > stable@vger.kernel.org. > > I hope this patch [1] is ok for you. > Sure. Acked that. Thanks. Regards, Sricharan
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi new file mode 100644 index 0000000..7c5d717 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, The Linux Foundation. All rights reserved. + +#include "qcom-ipq4019.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1"; + compatible = "qcom,ipq4019"; + + aliases { + serial0 = &blsp1_uart1; + serial1 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256MB */ + }; + + soc { + pinctrl@1000000 { + serial_0_pins: serial0_pinmux { + mux { + pins = "gpio16", "gpio17"; + function = "blsp_uart0"; + bias-disable; + }; + }; + + serial_1_pins: serial1_pinmux { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_uart1"; + bias-disable; + }; + }; + + spi_0_pins: spi_0_pinmux { + pinmux { + function = "blsp_spi0"; + pins = "gpio13", "gpio14", "gpio15"; + bias-disable; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio12"; + bias-disable; + output-high; + }; + }; + + i2c_0_pins: i2c_0_pinmux { + mux { + pins = "gpio20", "gpio21"; + function = "blsp_i2c0"; + bias-disable; + }; + }; + + nand_pins: nand_pins { + mux { + pins = "gpio53", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", + "gpio60", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68", "gpio69"; + function = "qpic"; + }; + }; + }; + + serial@78af000 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "ok"; + }; + + serial@78b0000 { + pinctrl-0 = <&serial_1_pins>; + pinctrl-names = "default"; + status = "ok"; + }; + + dma@7884000 { + status = "ok"; + }; + + spi@78b5000 { /* BLSP1 QUP1 */ + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "ok"; + cs-gpios = <&tlmm 12 0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "n25q128a11"; + spi-max-frequency = <24000000>; + }; + }; + + pci@40000000 { + status = "ok"; + perst-gpio = <&tlmm 38 0x1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 1c3b0ff..41a213a 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -307,7 +307,7 @@ dma-names = "rx", "tx"; }; - serial@78b0000 { + blsp1_uart2: serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78b0000 0x200>; interrupts = <0 108 0>;