diff mbox

[for-rc] RDMA/hns: Add 64KB page size support for hip08

Message ID 1526027483-47396-1-git-send-email-liuyixian@huawei.com (mailing list archive)
State Accepted
Delegated to: Jason Gunthorpe
Headers show

Commit Message

Yixian Liu May 11, 2018, 8:31 a.m. UTC
This patch adds the support of 64KB page size for hip08
in kernel.

Signed-off-by: Yixian Liu <liuyixian@huawei.com>
---
 drivers/infiniband/hw/hns/hns_roce_device.h |  3 +++
 drivers/infiniband/hw/hns/hns_roce_hw_v2.c  | 36 ++++++++++++++++-------------
 drivers/infiniband/hw/hns/hns_roce_mr.c     |  6 -----
 3 files changed, 23 insertions(+), 22 deletions(-)

Comments

Jason Gunthorpe May 16, 2018, 7:24 p.m. UTC | #1
On Fri, May 11, 2018 at 04:31:23PM +0800, Yixian Liu wrote:
> This patch adds the support of 64KB page size for hip08
> in kernel.
> 
> Signed-off-by: Yixian Liu <liuyixian@huawei.com>
>  drivers/infiniband/hw/hns/hns_roce_device.h |  3 +++
>  drivers/infiniband/hw/hns/hns_roce_hw_v2.c  | 36 ++++++++++++++++-------------
>  drivers/infiniband/hw/hns/hns_roce_mr.c     |  6 -----
>  3 files changed, 23 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h
> index fb305b7..53c2f1b 100644
> +++ b/drivers/infiniband/hw/hns/hns_roce_device.h
> @@ -100,6 +100,9 @@
>  #define SERV_TYPE_UC				2
>  #define SERV_TYPE_UD				3
>  
> +/* Configure to HW for PAGE_SIZE larger than 4KB */
> +#define PG_SHIFT_OFFSET				(PAGE_SHIFT - 12)

What happens if the kernel is built with PAGE_SHIFT < 12?

I'm guessing this needs a BUILD_BUG_ON as this HW cannot support that??

Jason
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Doug Ledford May 16, 2018, 8:04 p.m. UTC | #2
On Wed, 2018-05-16 at 13:24 -0600, Jason Gunthorpe wrote:
> On Fri, May 11, 2018 at 04:31:23PM +0800, Yixian Liu wrote:
> > This patch adds the support of 64KB page size for hip08
> > in kernel.
> > 
> > Signed-off-by: Yixian Liu <liuyixian@huawei.com>
> >  drivers/infiniband/hw/hns/hns_roce_device.h |  3 +++
> >  drivers/infiniband/hw/hns/hns_roce_hw_v2.c  | 36 ++++++++++++++++-------------
> >  drivers/infiniband/hw/hns/hns_roce_mr.c     |  6 -----
> >  3 files changed, 23 insertions(+), 22 deletions(-)
> > 
> > diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h
> > index fb305b7..53c2f1b 100644
> > +++ b/drivers/infiniband/hw/hns/hns_roce_device.h
> > @@ -100,6 +100,9 @@
> >  #define SERV_TYPE_UC				2
> >  #define SERV_TYPE_UD				3
> >  
> > +/* Configure to HW for PAGE_SIZE larger than 4KB */
> > +#define PG_SHIFT_OFFSET				(PAGE_SHIFT - 12)
> 
> What happens if the kernel is built with PAGE_SHIFT < 12?
> 
> I'm guessing this needs a BUILD_BUG_ON as this HW cannot support that??

I don't think the kernel supports less than a 4k page size.  Using git
grep "#define PAGE_SIZE" returns all the current possible page size
values on all arches and none that I saw were less than 12.
Yixian Liu May 17, 2018, 1:45 a.m. UTC | #3
On 2018/5/17 4:04, Doug Ledford wrote:
> On Wed, 2018-05-16 at 13:24 -0600, Jason Gunthorpe wrote:
>> On Fri, May 11, 2018 at 04:31:23PM +0800, Yixian Liu wrote:
>>> This patch adds the support of 64KB page size for hip08
>>> in kernel.
>>>
>>> Signed-off-by: Yixian Liu <liuyixian@huawei.com>
>>>  drivers/infiniband/hw/hns/hns_roce_device.h |  3 +++
>>>  drivers/infiniband/hw/hns/hns_roce_hw_v2.c  | 36 ++++++++++++++++-------------
>>>  drivers/infiniband/hw/hns/hns_roce_mr.c     |  6 -----
>>>  3 files changed, 23 insertions(+), 22 deletions(-)
>>>
>>> diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h
>>> index fb305b7..53c2f1b 100644
>>> +++ b/drivers/infiniband/hw/hns/hns_roce_device.h
>>> @@ -100,6 +100,9 @@
>>>  #define SERV_TYPE_UC				2
>>>  #define SERV_TYPE_UD				3
>>>  
>>> +/* Configure to HW for PAGE_SIZE larger than 4KB */
>>> +#define PG_SHIFT_OFFSET				(PAGE_SHIFT - 12)
>>
>> What happens if the kernel is built with PAGE_SHIFT < 12?
>>
>> I'm guessing this needs a BUILD_BUG_ON as this HW cannot support that??
> 
> I don't think the kernel supports less than a 4k page size.  Using git
> grep "#define PAGE_SIZE" returns all the current possible page size
> values on all arches and none that I saw were less than 12.
> 

That's right. I also think there is no case for PAGE_SHIFT less than 12.

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Jason Gunthorpe May 17, 2018, 3:45 a.m. UTC | #4
On Fri, May 11, 2018 at 04:31:23PM +0800, Yixian Liu wrote:
> This patch adds the support of 64KB page size for hip08
> in kernel.
> 
> Signed-off-by: Yixian Liu <liuyixian@huawei.com>
> ---
>  drivers/infiniband/hw/hns/hns_roce_device.h |  3 +++
>  drivers/infiniband/hw/hns/hns_roce_hw_v2.c  | 36 ++++++++++++++++-------------
>  drivers/infiniband/hw/hns/hns_roce_mr.c     |  6 -----
>  3 files changed, 23 insertions(+), 22 deletions(-)

Applied to for-next, thanks

I see this was marked as for-rc, but I think it is too late in the
cycle to add something that essentially looks like a new feature, even
if it is kind of fixing a bug. If the commit message was much better
justifying why this needed to be -rc then maybe it would have been OK.

Jason
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diff mbox

Patch

diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h
index fb305b7..53c2f1b 100644
--- a/drivers/infiniband/hw/hns/hns_roce_device.h
+++ b/drivers/infiniband/hw/hns/hns_roce_device.h
@@ -100,6 +100,9 @@ 
 #define SERV_TYPE_UC				2
 #define SERV_TYPE_UD				3
 
+/* Configure to HW for PAGE_SIZE larger than 4KB */
+#define PG_SHIFT_OFFSET				(PAGE_SHIFT - 12)
+
 #define PAGES_SHIFT_8				8
 #define PAGES_SHIFT_16				16
 #define PAGES_SHIFT_24				24
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index 8b84ab7..2c827be 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -1017,40 +1017,40 @@  static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
 
 	roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M,
 		       CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S,
-		       hr_dev->caps.qpc_ba_pg_sz);
+		       hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET);
 	roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M,
 		       CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S,
-		       hr_dev->caps.qpc_buf_pg_sz);
+		       hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET);
 	roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M,
 		       CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S,
 		       qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num);
 
 	roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M,
 		       CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S,
-		       hr_dev->caps.srqc_ba_pg_sz);
+		       hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET);
 	roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M,
 		       CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S,
-		       hr_dev->caps.srqc_buf_pg_sz);
+		       hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET);
 	roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M,
 		       CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S,
 		       srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num);
 
 	roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M,
 		       CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S,
-		       hr_dev->caps.cqc_ba_pg_sz);
+		       hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET);
 	roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M,
 		       CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S,
-		       hr_dev->caps.cqc_buf_pg_sz);
+		       hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET);
 	roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M,
 		       CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S,
 		       cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num);
 
 	roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M,
 		       CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S,
-		       hr_dev->caps.mpt_ba_pg_sz);
+		       hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET);
 	roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M,
 		       CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S,
-		       hr_dev->caps.mpt_buf_pg_sz);
+		       hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET);
 	roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M,
 		       CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,
 		       mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);
@@ -1344,7 +1344,8 @@  static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
 		       HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num);
 	roce_set_field(mpt_entry->byte_4_pd_hop_st,
 		       V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
-		       V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, mr->pbl_ba_pg_sz);
+		       V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
+		       mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
 	roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
 		       V2_MPT_BYTE_4_PD_S, mr->pd);
 	mpt_entry->byte_4_pd_hop_st = cpu_to_le32(mpt_entry->byte_4_pd_hop_st);
@@ -1418,7 +1419,8 @@  static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
 
 	roce_set_field(mpt_entry->byte_64_buf_pa1,
 		       V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
-		       V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, mr->pbl_buf_pg_sz);
+		       V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
+		       mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
 	mpt_entry->byte_64_buf_pa1 = cpu_to_le32(mpt_entry->byte_64_buf_pa1);
 
 	return 0;
@@ -1599,11 +1601,11 @@  static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
 	roce_set_field(cq_context->byte_24_pgsz_addr,
 		       V2_CQC_BYTE_24_CQE_BA_PG_SZ_M,
 		       V2_CQC_BYTE_24_CQE_BA_PG_SZ_S,
-		       hr_dev->caps.cqe_ba_pg_sz);
+		       hr_dev->caps.cqe_ba_pg_sz + PG_SHIFT_OFFSET);
 	roce_set_field(cq_context->byte_24_pgsz_addr,
 		       V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M,
 		       V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S,
-		       hr_dev->caps.cqe_buf_pg_sz);
+		       hr_dev->caps.cqe_buf_pg_sz + PG_SHIFT_OFFSET);
 
 	cq_context->cqe_ba = (u32)(dma_handle >> 3);
 
@@ -2699,7 +2701,7 @@  static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
 	roce_set_field(context->byte_16_buf_ba_pg_sz,
 		       V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
 		       V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S,
-		       hr_dev->caps.mtt_ba_pg_sz);
+		       hr_dev->caps.mtt_ba_pg_sz + PG_SHIFT_OFFSET);
 	roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
 		       V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
 		       V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0);
@@ -2707,7 +2709,7 @@  static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
 	roce_set_field(context->byte_16_buf_ba_pg_sz,
 		       V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
 		       V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S,
-		       hr_dev->caps.mtt_buf_pg_sz);
+		       hr_dev->caps.mtt_buf_pg_sz + PG_SHIFT_OFFSET);
 	roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
 		       V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
 		       V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0);
@@ -4140,12 +4142,14 @@  static void hns_roce_config_eqc(struct hns_roce_dev *hr_dev,
 	/* set eqe_ba_pg_sz */
 	roce_set_field(eqc->byte_8,
 		       HNS_ROCE_EQC_BA_PG_SZ_M,
-		       HNS_ROCE_EQC_BA_PG_SZ_S, eq->eqe_ba_pg_sz);
+		       HNS_ROCE_EQC_BA_PG_SZ_S,
+		       eq->eqe_ba_pg_sz + PG_SHIFT_OFFSET);
 
 	/* set eqe_buf_pg_sz */
 	roce_set_field(eqc->byte_8,
 		       HNS_ROCE_EQC_BUF_PG_SZ_M,
-		       HNS_ROCE_EQC_BUF_PG_SZ_S, eq->eqe_buf_pg_sz);
+		       HNS_ROCE_EQC_BUF_PG_SZ_S,
+		       eq->eqe_buf_pg_sz + PG_SHIFT_OFFSET);
 
 	/* set eq_producer_idx */
 	roce_set_field(eqc->byte_8,
diff --git a/drivers/infiniband/hw/hns/hns_roce_mr.c b/drivers/infiniband/hw/hns/hns_roce_mr.c
index f7256d8..d1fe0e7 100644
--- a/drivers/infiniband/hw/hns/hns_roce_mr.c
+++ b/drivers/infiniband/hw/hns/hns_roce_mr.c
@@ -1007,12 +1007,6 @@  struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
 	}
 
 	n = ib_umem_page_count(mr->umem);
-	if (mr->umem->page_shift != HNS_ROCE_HEM_PAGE_SHIFT) {
-		dev_err(dev, "Just support 4K page size but is 0x%lx now!\n",
-			BIT(mr->umem->page_shift));
-		ret = -EINVAL;
-		goto err_umem;
-	}
 
 	if (!hr_dev->caps.pbl_hop_num) {
 		if (n > HNS_ROCE_MAX_MTPT_PBL_NUM) {