@@ -879,6 +879,8 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev)
WREG32(VM_CONTEXT1_CNTL, 0);
evergreen_pcie_gart_tlb_flush(rdev);
+ DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
+ (unsigned)(rdev->mc.gtt_size >> 20), rdev->gart.table_addr);
rdev->gart.ready = true;
return 0;
}
@@ -991,6 +991,8 @@ int cayman_pcie_gart_enable(struct radeon_device *rdev)
WREG32(VM_CONTEXT1_CNTL, 0);
cayman_pcie_gart_tlb_flush(rdev);
+ DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
+ (unsigned)(rdev->mc.gtt_size >> 20), rdev->gart.table_addr);
rdev->gart.ready = true;
return 0;
}
@@ -513,6 +513,8 @@ int r100_pci_gart_enable(struct radeon_device *rdev)
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
WREG32(RADEON_AIC_CNTL, tmp);
r100_pci_gart_tlb_flush(rdev);
+ DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
+ (unsigned)(rdev->mc.gtt_size >> 20), rdev->gart.table_addr);
rdev->gart.ready = true;
return 0;
}
@@ -986,6 +986,8 @@ int r600_pcie_gart_enable(struct radeon_device *rdev)
WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
r600_pcie_gart_tlb_flush(rdev);
+ DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
+ (unsigned)(rdev->mc.gtt_size >> 20), rdev->gart.table_addr);
rdev->gart.ready = true;
return 0;
}
@@ -142,7 +142,7 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
u64 page_base;
if (!rdev->gart.ready) {
- WARN(1, "trying to unbind memory to unitialized GART !\n");
+ WARN(1, "trying to unbind memory to uninitialized GART !\n");
return;
}
t = offset / RADEON_GPU_PAGE_SIZE;
@@ -174,7 +174,7 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
int i, j;
if (!rdev->gart.ready) {
- WARN(1, "trying to bind memory to unitialized GART !\n");
+ WARN(1, "trying to bind memory to uninitialized GART !\n");
return -EINVAL;
}
t = offset / RADEON_GPU_PAGE_SIZE;
@@ -182,6 +182,8 @@ int rs400_gart_enable(struct radeon_device *rdev)
/* Enable gart */
WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
rs400_gart_tlb_flush(rdev);
+ DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
+ (unsigned)(rdev->mc.gtt_size >> 20), rdev->gart.table_addr);
rdev->gart.ready = true;
return 0;
}
@@ -484,6 +484,8 @@ int rs600_gart_enable(struct radeon_device *rdev)
tmp = RREG32_MC(R_000009_MC_CNTL1);
WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
rs600_gart_tlb_flush(rdev);
+ DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
+ (unsigned)(rdev->mc.gtt_size >> 20), rdev->gart.table_addr);
rdev->gart.ready = true;
return 0;
}
@@ -158,6 +158,8 @@ int rv770_pcie_gart_enable(struct radeon_device *rdev)
WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
r600_pcie_gart_tlb_flush(rdev);
+ DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
+ (unsigned)(rdev->mc.gtt_size >> 20), rdev->gart.table_addr);
rdev->gart.ready = true;
return 0;
}