| Message ID | 20180611081853.31474-1-thierry.reding@gmail.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
On Mon, Jun 11, 2018 at 10:18:53AM +0200, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > By default, the vic03 clock is a child of pll_m but that runs at 924 MHz > which is too fast for VIC. Make vic03 a child of pll_c3 by default so it > will run at a supported frequency. > > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > drivers/clk/tegra/clk-tegra124.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c > index 0c69c7970950..f5048f82c0b9 100644 > --- a/drivers/clk/tegra/clk-tegra124.c > +++ b/drivers/clk/tegra/clk-tegra124.c > @@ -1290,6 +1290,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = { > { TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 }, > { TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 }, > { TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 }, > + { TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 }, > /* must be the last entry */ > { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 }, > }; Adding Peter for visibility. Thierry
On Mon, Jun 11, 2018 at 10:22:44AM +0200, Thierry Reding wrote: > On Mon, Jun 11, 2018 at 10:18:53AM +0200, Thierry Reding wrote: > > From: Thierry Reding <treding@nvidia.com> > > > > By default, the vic03 clock is a child of pll_m but that runs at 924 MHz > > which is too fast for VIC. Make vic03 a child of pll_c3 by default so it > > will run at a supported frequency. > > > > Signed-off-by: Thierry Reding <treding@nvidia.com> > > --- > > drivers/clk/tegra/clk-tegra124.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c > > index 0c69c7970950..f5048f82c0b9 100644 > > --- a/drivers/clk/tegra/clk-tegra124.c > > +++ b/drivers/clk/tegra/clk-tegra124.c > > @@ -1290,6 +1290,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = { > > { TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 }, > > { TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 }, > > { TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 }, > > + { TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 }, > > /* must be the last entry */ > > { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 }, > > }; > > Adding Peter for visibility. I think we should consider using the Assigned clock parents and rate feature of the DT clock binding. Peter. -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, Jun 12, 2018 at 06:40:25PM +0300, Peter De Schrijver wrote: > On Mon, Jun 11, 2018 at 10:22:44AM +0200, Thierry Reding wrote: > > On Mon, Jun 11, 2018 at 10:18:53AM +0200, Thierry Reding wrote: > > > From: Thierry Reding <treding@nvidia.com> > > > > > > By default, the vic03 clock is a child of pll_m but that runs at 924 MHz > > > which is too fast for VIC. Make vic03 a child of pll_c3 by default so it > > > will run at a supported frequency. > > > > > > Signed-off-by: Thierry Reding <treding@nvidia.com> > > > --- > > > drivers/clk/tegra/clk-tegra124.c | 1 + > > > 1 file changed, 1 insertion(+) > > > > > > diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c > > > index 0c69c7970950..f5048f82c0b9 100644 > > > --- a/drivers/clk/tegra/clk-tegra124.c > > > +++ b/drivers/clk/tegra/clk-tegra124.c > > > @@ -1290,6 +1290,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = { > > > { TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 }, > > > { TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 }, > > > { TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 }, > > > + { TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 }, > > > /* must be the last entry */ > > > { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 }, > > > }; > > > > Adding Peter for visibility. > > I think we should consider using the Assigned clock parents and rate feature > of the DT clock binding. I'm sure we could do that, but it'd also be completely inconsistent with what we've done so far. These init tables effectively do the same thing as the assigned parents and rate bindings, only they predate them and we have done it this way essentially forever. I think there's some benefit in moving to the new bindings, but perhaps it'd make more sense to do it for Tegra186 and later because we don't have any of these initialization tables there yet and we don't even have a custom driver like this. Thierry
Quoting Thierry Reding (2018-06-11 01:18:53) > From: Thierry Reding <treding@nvidia.com> > > By default, the vic03 clock is a child of pll_m but that runs at 924 MHz > which is too fast for VIC. Make vic03 a child of pll_c3 by default so it > will run at a supported frequency. > > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- Applied to clk-next -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 0c69c7970950..f5048f82c0b9 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1290,6 +1290,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = { { TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 }, { TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 }, { TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 }, + { TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 }, /* must be the last entry */ { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 }, };