| Message ID | 1529587815-23420-1-git-send-email-vandita.kulkarni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
tor 2018-06-21 klockan 19:00 +0530 skrev Vandita Kulkarni: > Alpha blending with alpha 0 and 0xff passes through > alpha math and rounding logic causing differences > compared to fully transparent or opaque plane,resulting > in CRC mismatch. > This WA on icl and above enables hardware to bypass alpha > math and rounding for per pixel alpha values of 00 and 0xff > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > --- Thanks, pushed with my r-b. :) > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ > drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index 4bfd7a9..6e59bfe 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7366,6 +7366,14 @@ enum { > #define BDW_SCRATCH1 _MMIO(0x > b11c) > #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2) > > +/*GEN11 chicken */ > +#define _PIPEA_CHICKEN 0x70038 > +#define _PIPEB_CHICKEN 0x71038 > +#define _PIPEC_CHICKEN 0x72038 > +#define PER_PIXEL_ALPHA_BYPASS_EN (1<<7) > +#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, > _PIPEA_CHICKEN,\ > + _PIPEB_CHICKEN) > + > /* PCH */ > > /* south display engine interrupt: IBX */ > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 2c8fef3..ca5882c 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct > intel_crtc_state *pipe_config, > struct intel_atomic_state *old_intel_state = > to_intel_atomic_state(old_state); > bool psl_clkgate_wa; > + u32 pipe_chicken; > > if (WARN_ON(intel_crtc->active)) > return; > @@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct > intel_crtc_state *pipe_config, > */ > intel_color_load_luts(&pipe_config->base); > > + /* > + * Display WA #1153: enable hardware to bypass the alpha > math > + * and rounding for per-pixel values 00 and 0xff > + */ > + if (INTEL_GEN(dev_priv) >= 11) { > + pipe_chicken = I915_READ(PIPE_CHICKEN(pipe)); > + if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN)) > + I915_WRITE_FW(PIPE_CHICKEN(pipe), > + pipe_chicken | > PER_PIXEL_ALPHA_BYPASS_EN); > + } > + > intel_ddi_set_pipe_settings(pipe_config); > if (!transcoder_is_dsi(cpu_transcoder)) > intel_ddi_enable_transcoder_func(pipe_config);
On Thu, Jun 21, 2018 at 07:00:15PM +0530, Vandita Kulkarni wrote: > Alpha blending with alpha 0 and 0xff passes through > alpha math and rounding logic causing differences > compared to fully transparent or opaque plane,resulting > in CRC mismatch. > This WA on icl and above enables hardware to bypass alpha > math and rounding for per pixel alpha values of 00 and 0xff > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ > drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 4bfd7a9..6e59bfe 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7366,6 +7366,14 @@ enum { > #define BDW_SCRATCH1 _MMIO(0xb11c) > #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2) > > +/*GEN11 chicken */ > +#define _PIPEA_CHICKEN 0x70038 > +#define _PIPEB_CHICKEN 0x71038 > +#define _PIPEC_CHICKEN 0x72038 > +#define PER_PIXEL_ALPHA_BYPASS_EN (1<<7) > +#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ > + _PIPEB_CHICKEN) > + > /* PCH */ > > /* south display engine interrupt: IBX */ > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 2c8fef3..ca5882c 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > struct intel_atomic_state *old_intel_state = > to_intel_atomic_state(old_state); > bool psl_clkgate_wa; > + u32 pipe_chicken; > > if (WARN_ON(intel_crtc->active)) > return; > @@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > */ > intel_color_load_luts(&pipe_config->base); > > + /* > + * Display WA #1153: enable hardware to bypass the alpha math > + * and rounding for per-pixel values 00 and 0xff > + */ This is an odd place for a register write. Why here instead of init_clock_gating()? > + if (INTEL_GEN(dev_priv) >= 11) { > + pipe_chicken = I915_READ(PIPE_CHICKEN(pipe)); > + if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN)) > + I915_WRITE_FW(PIPE_CHICKEN(pipe), > + pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN); That check for the bit already being set is quite pointless. > + } > + > intel_ddi_set_pipe_settings(pipe_config); > if (!transcoder_is_dsi(cpu_transcoder)) > intel_ddi_enable_transcoder_func(pipe_config); > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> -----Original Message----- > From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] > Sent: Friday, June 22, 2018 12:42 AM > To: Kulkarni, Vandita <vandita.kulkarni@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten > <maarten.lankhorst@intel.com> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Enable hw workaround to bypass > alpha > > On Thu, Jun 21, 2018 at 07:00:15PM +0530, Vandita Kulkarni wrote: > > Alpha blending with alpha 0 and 0xff passes through alpha math and > > rounding logic causing differences compared to fully transparent or > > opaque plane,resulting in CRC mismatch. > > This WA on icl and above enables hardware to bypass alpha math and > > rounding for per pixel alpha values of 00 and 0xff > > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ > > drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ > > 2 files changed, 20 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h index 4bfd7a9..6e59bfe 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -7366,6 +7366,14 @@ enum { > > #define BDW_SCRATCH1 > _MMIO(0xb11c) > > #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << > 2) > > > > +/*GEN11 chicken */ > > +#define _PIPEA_CHICKEN 0x70038 > > +#define _PIPEB_CHICKEN 0x71038 > > +#define _PIPEC_CHICKEN 0x72038 > > +#define PER_PIXEL_ALPHA_BYPASS_EN (1<<7) > > +#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, > _PIPEA_CHICKEN,\ > > + _PIPEB_CHICKEN) > > + > > /* PCH */ > > > > /* south display engine interrupt: IBX */ diff --git > > a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 2c8fef3..ca5882c 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct > intel_crtc_state *pipe_config, > > struct intel_atomic_state *old_intel_state = > > to_intel_atomic_state(old_state); > > bool psl_clkgate_wa; > > + u32 pipe_chicken; > > > > if (WARN_ON(intel_crtc->active)) > > return; > > @@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct > intel_crtc_state *pipe_config, > > */ > > intel_color_load_luts(&pipe_config->base); > > > > + /* > > + * Display WA #1153: enable hardware to bypass the alpha math > > + * and rounding for per-pixel values 00 and 0xff > > + */ > > This is an odd place for a register write. Why here instead of > init_clock_gating()? This reg is per pipe. The macro takes pipe num. Also I am not sure if it is ok to write alpha related WA in init_clock_gating. I couldn't find more appropriate place to add this. Hence I added it here. > > > + if (INTEL_GEN(dev_priv) >= 11) { > > + pipe_chicken = I915_READ(PIPE_CHICKEN(pipe)); > > + if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN)) > > + I915_WRITE_FW(PIPE_CHICKEN(pipe), > > + pipe_chicken | > PER_PIXEL_ALPHA_BYPASS_EN); > > That check for the bit already being set is quite pointless. Since we are not disabling it, not to write it again if enabled, this check is added. > > > + } > > + > > intel_ddi_set_pipe_settings(pipe_config); > > if (!transcoder_is_dsi(cpu_transcoder)) > > intel_ddi_enable_transcoder_func(pipe_config); > > -- > > 1.9.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4bfd7a9..6e59bfe 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7366,6 +7366,14 @@ enum { #define BDW_SCRATCH1 _MMIO(0xb11c) #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2) +/*GEN11 chicken */ +#define _PIPEA_CHICKEN 0x70038 +#define _PIPEB_CHICKEN 0x71038 +#define _PIPEC_CHICKEN 0x72038 +#define PER_PIXEL_ALPHA_BYPASS_EN (1<<7) +#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ + _PIPEB_CHICKEN) + /* PCH */ /* south display engine interrupt: IBX */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2c8fef3..ca5882c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, struct intel_atomic_state *old_intel_state = to_intel_atomic_state(old_state); bool psl_clkgate_wa; + u32 pipe_chicken; if (WARN_ON(intel_crtc->active)) return; @@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, */ intel_color_load_luts(&pipe_config->base); + /* + * Display WA #1153: enable hardware to bypass the alpha math + * and rounding for per-pixel values 00 and 0xff + */ + if (INTEL_GEN(dev_priv) >= 11) { + pipe_chicken = I915_READ(PIPE_CHICKEN(pipe)); + if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN)) + I915_WRITE_FW(PIPE_CHICKEN(pipe), + pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN); + } + intel_ddi_set_pipe_settings(pipe_config); if (!transcoder_is_dsi(cpu_transcoder)) intel_ddi_enable_transcoder_func(pipe_config);
Alpha blending with alpha 0 and 0xff passes through alpha math and rounding logic causing differences compared to fully transparent or opaque plane,resulting in CRC mismatch. This WA on icl and above enables hardware to bypass alpha math and rounding for per pixel alpha values of 00 and 0xff Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ 2 files changed, 20 insertions(+)