| Message ID | 20180613161314.14894-2-yixun.lan@amlogic.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
Hello Yixun, Hello Liang, I have a few small comments inline below additionally I tried to explain the reason behind "amlogic,mmc-syscon", clkin0 and clkin1 so Rob (or the devicetree maintainers in general) can give feedback. feel free to correct me wherever I'm wrong or provide additional notes in case I missed something! On Wed, Jun 13, 2018 at 10:17 AM Yixun Lan <yixun.lan@amlogic.com> wrote: > > From: Liang Yang <liang.yang@amlogic.com> > > Add Amlogic NAND controller dt-bindings for Meson SoC, > Current this driver support GXBB/GXL/AXG platform. > > Signed-off-by: Liang Yang <liang.yang@amlogic.com> > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > --- > .../bindings/mtd/amlogic,meson-nand.txt | 118 ++++++++++++++++++ > 1 file changed, 118 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt > > diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt > new file mode 100644 > index 000000000000..eac9f9433d5d > --- /dev/null > +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt > @@ -0,0 +1,118 @@ > +Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs > + > +This file documents the properties in addition to those available in > +the MTD NAND bindings. > + > +Required properties: > +- compatible : contains one of: > + - "amlogic,meson-gxl-nfc" > + - "amlogic,meson-axg-nfc" the patch description states that GXBB/GXL/AXG are supported shouldn't you add a compatible string for GXBB as well? > +- clocks : > + A list of phandle + clock-specifier pairs for the clocks listed > + in clock-names. > + > +- clock-names: Should contain the following: > + "core" - NFC module gate clock > + "clkin0" - Parent clock of internal mux > + "clkin1" - Other parent clock of internal mux to give the devicetree maintainers some context on clkin0 and clkin1: older SoCs (Meson8, Meson8b - not supported by this binding/driver yet) had a dedicated NAND clock. there neither clkin0 or clkin1 would be used, instead we just had a "nand" or "interface" clock (I'm not aware of the actual naming in Amlogic's internal datasheets) newer SoCs do NOT have a dedicated NAND "interface" clock anymore. instead they are sharing the clock with the "sd_emmc_c" controller (I *believe* the reason for this is because sd_emmc_c and the NAND controller use the same pads on the SoC, pinctrl muxing controls where these pads are routed -> NAND and sd_emmc_c cannot be used at the same time, so SoC designers probably decided to re-use the clock) unfortunately the sd_emmc_c clock is not provided by the "main" clock controller on these newer SoCs instead the clock is part of the MMC controller's register space (see the SD_EMMC_CLOCK register in drivers/mmc/host/meson-gx-mmc.c) even worse: the SD_EMMC_CLOCK contains more than just clock settings (bit 25 enables the SDIO interrupt, which is currently not supported by the meson-gx-mmc driver though) the SD_EMMC_CLOCK register has a mux (CLK_SRC_MASK) to choose from clkin0 and clkin1 which are passed here the "amlogic,mmc-syscon" property is used to get a phandle to the sd_emmc_c syscon register space thus there is a bit of code duplication in the MMC and NAND drivers with this binding (because both need to configure the SD_EMMC_CLOCK register) > + > +- pins : Select pins which NFC need. > +- nand_pins: Detail NAND pins information. > + nand_pins: nand { > + mux { > + groups = "emmc_nand_d0", > + "emmc_nand_d1", > + "emmc_nand_d2", > + "emmc_nand_d3", > + "emmc_nand_d4", > + "emmc_nand_d5", > + "emmc_nand_d6", > + "emmc_nand_d7", > + "nand_ce0", > + "nand_rb0", > + "nand_ale", > + "nand_cle", > + "nand_wen_clk", > + "nand_ren_wr"; > + function = "nand"; > + }; > + }; > + > +- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC > + controller port C > + > +Optional children nodes: > +Children nodes represent the available nand chips. > + > +Optional properties: > +- meson-nand-user-mode : > + only set 2 or 16 which mean the way of reading OOB bytes by NFC. as far as I know vendor specific properties should follow the naming schema "vendor,purpose" in this case this would be "amlogic,nand-user-mode" maybe Rob can comment on this? > +- meson-nand-ran-mode : > + setting 0 or 1, means disable/enable scrambler which keeps the balence > + of 0 and 1 I assume 0 and 1 are the only possible values. to use of_property_read_bool in the driver the property would be either: - (absent) = scrambler is disabled - amlogic,nand-enable-scrambler (without any value - also same comment as above for the value) = scrambler is enabled Regards Martin
Hi Yixun, On Wed, 13 Jun 2018 16:13:13 +0000 Yixun Lan <yixun.lan@amlogic.com> wrote: > From: Liang Yang <liang.yang@amlogic.com> > > Add Amlogic NAND controller dt-bindings for Meson SoC, > Current this driver support GXBB/GXL/AXG platform. > > Signed-off-by: Liang Yang <liang.yang@amlogic.com> > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > --- > .../bindings/mtd/amlogic,meson-nand.txt | 118 ++++++++++++++++++ > 1 file changed, 118 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt > > diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt > new file mode 100644 > index 000000000000..eac9f9433d5d > --- /dev/null > +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt > @@ -0,0 +1,118 @@ > +Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs > + > +This file documents the properties in addition to those available in > +the MTD NAND bindings. > + > +Required properties: > +- compatible : contains one of: > + - "amlogic,meson-gxl-nfc" > + - "amlogic,meson-axg-nfc" > +- clocks : > + A list of phandle + clock-specifier pairs for the clocks listed > + in clock-names. > + > +- clock-names: Should contain the following: > + "core" - NFC module gate clock > + "clkin0" - Parent clock of internal mux > + "clkin1" - Other parent clock of internal mux > + > +- pins : Select pins which NFC need. > +- nand_pins: Detail NAND pins information. > + nand_pins: nand { > + mux { > + groups = "emmc_nand_d0", > + "emmc_nand_d1", > + "emmc_nand_d2", > + "emmc_nand_d3", > + "emmc_nand_d4", > + "emmc_nand_d5", > + "emmc_nand_d6", > + "emmc_nand_d7", > + "nand_ce0", > + "nand_rb0", > + "nand_ale", > + "nand_cle", > + "nand_wen_clk", > + "nand_ren_wr"; > + function = "nand"; > + }; > + }; Not sure, but I think you can drop the pinmux description. > + > +- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC > + controller port C > + > +Optional children nodes: > +Children nodes represent the available nand chips. > + > +Optional properties: > +- meson-nand-user-mode : > + only set 2 or 16 which mean the way of reading OOB bytes by NFC. I haven't checked the driver but this prop looks like a reg field value you're directly copying in the reg at init time. We usually avoid exposing such details in the DT. I'm not even sure you should have a property to select how you want to read OOB (need to check the driver before giving a definitive answer on this aspect). > +- meson-nand-ran-mode : > + setting 0 or 1, means disable/enable scrambler which keeps the balence > + of 0 and 1 You don't need that one. The NAND chip will tell you whether it requires scrambling or not (see NAND_NEED_SCRAMBLING [1]). > + > +Other properties: > +see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings. > + > +Example demonstrate on AXG SoC: > + > + sd_emmc_c: mmc@7000 { > + compatible = "simple-bus", "syscon"; > + reg = <0x0 0x7000 0x0 0x800>; > + status = "okay"; > + }; > + > + nand: nfc@7800 { > + compatible = "amlogic,meson-axg-nfc"; > + reg = <0x0 0x7800 0x0 0x100>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; > + status = "disabled"; > + clocks = <&clkc CLKID_SD_EMMC_C>, > + <&clkc CLKID_SD_EMMC_C_CLK0>, > + <&clkc CLKID_FCLK_DIV2>; > + clock-names = "core", "clkin0", "clkin1"; > + amlogic,mmc-syscon = <&sd_mmc_c>; > + > + status = "okay"; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&nand_pins>; > + > + nand@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + nand-on-flash-bbt; > + nand-ecc-mode = "hw"; > + nand-ecc-strength = <8>; > + nand-ecc-step-size = <1024>; > + > + meson-nand-user-mode = <2>; > + meson-nand-ran-mode = <1>; > + > + partition@0 { > + label = "boot"; > + reg = <0x00000000 0x00200000>; > + read-only; > + }; > + partition@200000 { > + label = "env"; > + reg = <0x00200000 0x00400000>; > + }; > + partition@600000 { > + label = "system"; > + reg = <0x00600000 0x00a00000>; > + }; > + partition@1000000 { > + label = "rootfs"; > + reg = <0x01000000 0x03000000>; > + }; > + partition@4000000 { > + label = "media"; > + reg = <0x04000000 0x8000000>; > + }; Partitions should be places in a "partitions" subnode: partitions { compatible = "fixed-partitions"; ... }; Also, I'm not sure you need to put that in your example. > + }; > + }; Regards, Boris
On Sun, Jun 24, 2018 at 12:46:59AM +0200, Martin Blumenstingl wrote: > Hello Yixun, Hello Liang, > > I have a few small comments inline below > additionally I tried to explain the reason behind > "amlogic,mmc-syscon", clkin0 and clkin1 so Rob (or the devicetree > maintainers in general) can give feedback. feel free to correct me > wherever I'm wrong or provide additional notes in case I missed > something! > > On Wed, Jun 13, 2018 at 10:17 AM Yixun Lan <yixun.lan@amlogic.com> wrote: > > > > From: Liang Yang <liang.yang@amlogic.com> > > > > Add Amlogic NAND controller dt-bindings for Meson SoC, > > Current this driver support GXBB/GXL/AXG platform. > > > > Signed-off-by: Liang Yang <liang.yang@amlogic.com> > > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > > --- > > .../bindings/mtd/amlogic,meson-nand.txt | 118 ++++++++++++++++++ > > 1 file changed, 118 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt > > > > diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt > > new file mode 100644 > > index 000000000000..eac9f9433d5d > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt > > @@ -0,0 +1,118 @@ > > +Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs > > + > > +This file documents the properties in addition to those available in > > +the MTD NAND bindings. > > + > > +Required properties: > > +- compatible : contains one of: > > + - "amlogic,meson-gxl-nfc" > > + - "amlogic,meson-axg-nfc" > the patch description states that GXBB/GXL/AXG are supported > shouldn't you add a compatible string for GXBB as well? > > > +- clocks : > > + A list of phandle + clock-specifier pairs for the clocks listed > > + in clock-names. > > + > > +- clock-names: Should contain the following: > > + "core" - NFC module gate clock > > + "clkin0" - Parent clock of internal mux > > + "clkin1" - Other parent clock of internal mux > to give the devicetree maintainers some context on clkin0 and clkin1: > > older SoCs (Meson8, Meson8b - not supported by this binding/driver > yet) had a dedicated NAND clock. there neither clkin0 or clkin1 would > be used, instead we just had a "nand" or "interface" clock (I'm not > aware of the actual naming in Amlogic's internal datasheets) > > newer SoCs do NOT have a dedicated NAND "interface" clock anymore. > instead they are sharing the clock with the "sd_emmc_c" controller (I > *believe* the reason for this is because sd_emmc_c and the NAND > controller use the same pads on the SoC, pinctrl muxing controls where > these pads are routed -> NAND and sd_emmc_c cannot be used at the same > time, so SoC designers probably decided to re-use the clock) > > unfortunately the sd_emmc_c clock is not provided by the "main" clock > controller on these newer SoCs > instead the clock is part of the MMC controller's register space (see > the SD_EMMC_CLOCK register in drivers/mmc/host/meson-gx-mmc.c) > even worse: the SD_EMMC_CLOCK contains more than just clock settings > (bit 25 enables the SDIO interrupt, which is currently not supported > by the meson-gx-mmc driver though) > > the SD_EMMC_CLOCK register has a mux (CLK_SRC_MASK) to choose from > clkin0 and clkin1 which are passed here > the "amlogic,mmc-syscon" property is used to get a phandle to the > sd_emmc_c syscon register space > thus there is a bit of code duplication in the MMC and NAND drivers > with this binding (because both need to configure the SD_EMMC_CLOCK > register) Well, that's ugly. Really, the SD controller should be modeled as a clock provider. But then you would have to always have a driver instantiated for it. Maybe you need that anyway if accessing this register is dependent on some other clock or reset to the module being enabled (which you may not hit if you only access the reg during boot)? But if you really want to do it this way, I guess that is fine. > > + > > +- pins : Select pins which NFC need. > > +- nand_pins: Detail NAND pins information. > > + nand_pins: nand { > > + mux { > > + groups = "emmc_nand_d0", > > + "emmc_nand_d1", > > + "emmc_nand_d2", > > + "emmc_nand_d3", > > + "emmc_nand_d4", > > + "emmc_nand_d5", > > + "emmc_nand_d6", > > + "emmc_nand_d7", > > + "nand_ce0", > > + "nand_rb0", > > + "nand_ale", > > + "nand_cle", > > + "nand_wen_clk", > > + "nand_ren_wr"; > > + function = "nand"; > > + }; > > + }; > > + > > +- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC > > + controller port C > > + > > +Optional children nodes: > > +Children nodes represent the available nand chips. > > + > > +Optional properties: > > +- meson-nand-user-mode : > > + only set 2 or 16 which mean the way of reading OOB bytes by NFC. > as far as I know vendor specific properties should follow the naming > schema "vendor,purpose" > in this case this would be "amlogic,nand-user-mode" > > maybe Rob can comment on this? Yes. > > > +- meson-nand-ran-mode : > > + setting 0 or 1, means disable/enable scrambler which keeps the balence > > + of 0 and 1 > I assume 0 and 1 are the only possible values. > to use of_property_read_bool in the driver the property would be either: > - (absent) = scrambler is disabled > - amlogic,nand-enable-scrambler (without any value - also same comment > as above for the value) = scrambler is enabled > > > Regards > Martin
Rob Herring <robh@kernel.org> writes: > On Sun, Jun 24, 2018 at 12:46:59AM +0200, Martin Blumenstingl wrote: >> Hello Yixun, Hello Liang, >> >> I have a few small comments inline below >> additionally I tried to explain the reason behind >> "amlogic,mmc-syscon", clkin0 and clkin1 so Rob (or the devicetree >> maintainers in general) can give feedback. feel free to correct me >> wherever I'm wrong or provide additional notes in case I missed >> something! >> >> On Wed, Jun 13, 2018 at 10:17 AM Yixun Lan <yixun.lan@amlogic.com> wrote: >> > >> > From: Liang Yang <liang.yang@amlogic.com> >> > >> > Add Amlogic NAND controller dt-bindings for Meson SoC, >> > Current this driver support GXBB/GXL/AXG platform. >> > >> > Signed-off-by: Liang Yang <liang.yang@amlogic.com> >> > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> >> > --- >> > .../bindings/mtd/amlogic,meson-nand.txt | 118 ++++++++++++++++++ >> > 1 file changed, 118 insertions(+) >> > create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt >> > >> > diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt >> > new file mode 100644 >> > index 000000000000..eac9f9433d5d >> > --- /dev/null >> > +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt >> > @@ -0,0 +1,118 @@ >> > +Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs >> > + >> > +This file documents the properties in addition to those available in >> > +the MTD NAND bindings. >> > + >> > +Required properties: >> > +- compatible : contains one of: >> > + - "amlogic,meson-gxl-nfc" >> > + - "amlogic,meson-axg-nfc" >> the patch description states that GXBB/GXL/AXG are supported >> shouldn't you add a compatible string for GXBB as well? >> >> > +- clocks : >> > + A list of phandle + clock-specifier pairs for the clocks listed >> > + in clock-names. >> > + >> > +- clock-names: Should contain the following: >> > + "core" - NFC module gate clock >> > + "clkin0" - Parent clock of internal mux >> > + "clkin1" - Other parent clock of internal mux >> to give the devicetree maintainers some context on clkin0 and clkin1: >> >> older SoCs (Meson8, Meson8b - not supported by this binding/driver >> yet) had a dedicated NAND clock. there neither clkin0 or clkin1 would >> be used, instead we just had a "nand" or "interface" clock (I'm not >> aware of the actual naming in Amlogic's internal datasheets) >> >> newer SoCs do NOT have a dedicated NAND "interface" clock anymore. >> instead they are sharing the clock with the "sd_emmc_c" controller (I >> *believe* the reason for this is because sd_emmc_c and the NAND >> controller use the same pads on the SoC, pinctrl muxing controls where >> these pads are routed -> NAND and sd_emmc_c cannot be used at the same >> time, so SoC designers probably decided to re-use the clock) >> >> unfortunately the sd_emmc_c clock is not provided by the "main" clock >> controller on these newer SoCs >> instead the clock is part of the MMC controller's register space (see >> the SD_EMMC_CLOCK register in drivers/mmc/host/meson-gx-mmc.c) >> even worse: the SD_EMMC_CLOCK contains more than just clock settings >> (bit 25 enables the SDIO interrupt, which is currently not supported >> by the meson-gx-mmc driver though) >> >> the SD_EMMC_CLOCK register has a mux (CLK_SRC_MASK) to choose from >> clkin0 and clkin1 which are passed here >> the "amlogic,mmc-syscon" property is used to get a phandle to the >> sd_emmc_c syscon register space >> thus there is a bit of code duplication in the MMC and NAND drivers >> with this binding (because both need to configure the SD_EMMC_CLOCK >> register) > > Well, that's ugly. Really, the SD controller should be modeled as a > clock provider. But then you would have to always have a driver > instantiated for it. Maybe you need that anyway if accessing this > register is dependent on some other clock or reset to the module being > enabled (which you may not hit if you only access the reg during boot)? On some earlier rounds of off-lis review, we did consider making the SD/MMC controller a clock provider. But forcing it to be instantiated was kinda ugly too, especailly because there are several instances of the MMC IP, and only one of them shares the clock with the NAND, so only one of them needs to be a clock provider. :( > But if you really want to do it this way, I guess that is fine. Thanks. We did consider a few options, and found this one to be the least worst of a few options. Kevin
diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt new file mode 100644 index 000000000000..eac9f9433d5d --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt @@ -0,0 +1,118 @@ +Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs + +This file documents the properties in addition to those available in +the MTD NAND bindings. + +Required properties: +- compatible : contains one of: + - "amlogic,meson-gxl-nfc" + - "amlogic,meson-axg-nfc" +- clocks : + A list of phandle + clock-specifier pairs for the clocks listed + in clock-names. + +- clock-names: Should contain the following: + "core" - NFC module gate clock + "clkin0" - Parent clock of internal mux + "clkin1" - Other parent clock of internal mux + +- pins : Select pins which NFC need. +- nand_pins: Detail NAND pins information. + nand_pins: nand { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "nand_ce0", + "nand_rb0", + "nand_ale", + "nand_cle", + "nand_wen_clk", + "nand_ren_wr"; + function = "nand"; + }; + }; + +- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC + controller port C + +Optional children nodes: +Children nodes represent the available nand chips. + +Optional properties: +- meson-nand-user-mode : + only set 2 or 16 which mean the way of reading OOB bytes by NFC. +- meson-nand-ran-mode : + setting 0 or 1, means disable/enable scrambler which keeps the balence + of 0 and 1 + +Other properties: +see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings. + +Example demonstrate on AXG SoC: + + sd_emmc_c: mmc@7000 { + compatible = "simple-bus", "syscon"; + reg = <0x0 0x7000 0x0 0x800>; + status = "okay"; + }; + + nand: nfc@7800 { + compatible = "amlogic,meson-axg-nfc"; + reg = <0x0 0x7800 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_CLK0>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + amlogic,mmc-syscon = <&sd_mmc_c>; + + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <1024>; + + meson-nand-user-mode = <2>; + meson-nand-ran-mode = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "env"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "system"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "rootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "media"; + reg = <0x04000000 0x8000000>; + }; + }; + };