| Message ID | 1530773430-57285-2-git-send-email-oulijun@huawei.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
Hi Lijun,
I love your patch! Perhaps something to improve:
[auto build test WARNING on rdma/for-next]
[also build test WARNING on v4.18-rc3 next-20180704]
[cannot apply to linus/master linux-sof-driver/master]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Lijun-Ou/Four-cmd-queues-support-and-sparse-checking/20180705-145936
base: https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git for-next
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__
sparse warnings: (new ones prefixed by >>)
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1608:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1608:9: sparse: invalid assignment: |=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1608:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1608:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1705:9: sparse: invalid assignment: &=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1705:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1705:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1705:9: sparse: invalid assignment: |=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1705:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1705:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1707:9: sparse: invalid assignment: &=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1707:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1707:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1707:9: sparse: invalid assignment: |=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1707:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1707:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1709:9: sparse: invalid assignment: &=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1709:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1709:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1709:9: sparse: invalid assignment: |=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1709:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1709:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1710:9: sparse: invalid assignment: &=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1710:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1710:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1710:9: sparse: invalid assignment: |=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1710:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1710:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1711:9: sparse: invalid assignment: &=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1711:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1711:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1711:9: sparse: invalid assignment: |=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1711:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1711:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1743:18: sparse: cast to restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1743:18: sparse: cast from restricted __be32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1812:9: sparse: invalid assignment: &=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1812:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1812:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1812:9: sparse: invalid assignment: |=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1812:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1812:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1827:9: sparse: invalid assignment: &=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1827:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1827:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1827:9: sparse: invalid assignment: |=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1827:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1827:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1874:32: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] virt_addr_l @@ got unsignrestricted __le32 [usertype] virt_addr_l @@
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1874:32: expected restricted __le32 [usertype] virt_addr_l
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1874:32: got unsigned int [unsigned] [usertype] <noident>
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1875:32: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] virt_addr_h @@ got unsignrestricted __le32 [usertype] virt_addr_h @@
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1875:32: expected restricted __le32 [usertype] virt_addr_h
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1875:32: got unsigned int [unsigned] [usertype] <noident>
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1876:27: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] length @@ got unsignrestricted __le32 [usertype] length @@
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1876:27: expected restricted __le32 [usertype] length
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1876:27: got unsigned int [unsigned] [usertype] <noident>
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1908:25: sparse: cast from restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1914:25: sparse: cast from restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1918:25: sparse: cast from restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1924:25: sparse: cast from restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1928:25: sparse: cast from restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1934:25: sparse: cast from restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1938:25: sparse: cast from restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1945:25: sparse: cast from restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1951:25: sparse: cast from restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1955:25: sparse: cast from restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1961:25: sparse: cast from restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1965:25: sparse: cast from restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1977:31: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] pbl_addr_l @@ got unsignrestricted __le32 [usertype] pbl_addr_l @@
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1977:31: expected restricted __le32 [usertype] pbl_addr_l
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1977:31: got unsigned int [unsigned] [usertype] <noident>
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2012:9: sparse: invalid assignment: &=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2012:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2012:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2012:9: sparse: invalid assignment: |=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2012:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2012:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2013:9: sparse: invalid assignment: &=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2013:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2013:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2013:9: sparse: invalid assignment: |=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2013:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2013:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2015:9: sparse: invalid assignment: &=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2015:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2015:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2015:9: sparse: invalid assignment: |=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2015:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2015:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2017:9: sparse: invalid assignment: &=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2017:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2017:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2017:9: sparse: invalid assignment: |=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2017:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2017:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2020:28: sparse: incorrect type in argument 1 (different base types) @@ expected restricted __le32 [usertype] *val @@ got 2 [usertype] *val @@
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2020:28: expected restricted __le32 [usertype] *val
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2020:28: got unsigned int *<noident>
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2107:34: sparse: cast from restricted __le32
>> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2109:29: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] cq_bt_l @@ got unsignrestricted __le32 [usertype] cq_bt_l @@
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2109:29: expected restricted __le32 [usertype] cq_bt_l
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2109:29: got unsigned int [unsigned] [usertype] <noident>
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2110:31: sparse: cast from restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2122:35: sparse: cast from restricted __le32
>> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2124:35: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] cur_cqe_ba0_l @@ got unsignrestricted __le32 [usertype] cur_cqe_ba0_l @@
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2124:35: expected restricted __le32 [usertype] cur_cqe_ba0_l
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2124:35: got unsigned int [unsigned] [usertype] <noident>
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2125:37: sparse: cast from restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2127:9: sparse: cast from restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2144:35: sparse: cast from restricted __le32
>> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2146:37: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] cqe_tptr_addr_l @@ got unsignrestricted __le32 [usertype] cqe_tptr_addr_l @@
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2146:37: expected restricted __le32 [usertype] cqe_tptr_addr_l
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2146:37: got unsigned int [unsigned] [usertype] <noident>
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2164:35: sparse: cast from restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2186:9: sparse: invalid assignment: &=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2186:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2186:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2186:9: sparse: invalid assignment: |=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2186:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2186:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2187:9: sparse: invalid assignment: &=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2187:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2187:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2187:9: sparse: invalid assignment: |=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2187:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2187:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2189:9: sparse: invalid assignment: &=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2189:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2189:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2189:9: sparse: invalid assignment: |=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2189:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2189:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2191:9: sparse: invalid assignment: &=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2191:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2191:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2191:9: sparse: invalid assignment: |=
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2191:9: left side has type unsigned int
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2191:9: right side has type restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2195:28: sparse: incorrect type in argument 1 (different base types) @@ expected restricted __le32 [usertype] *val @@ got 2 [usertype] *val @@
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2195:28: expected restricted __le32 [usertype] *val
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2195:28: got unsigned int *<noident>
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2363:33: sparse: cast to restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2363:33: sparse: cast from restricted __be32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2363:33: sparse: cast to restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2363:33: sparse: cast from restricted __be32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2363:33: sparse: cast to restricted __le32
drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2363:33: sparse: too many warnings
include/linux/slab.h:631:13: sparse: undefined identifier '__builtin_mul_overflow'
include/linux/slab.h:631:13: sparse: not a function <noident>
include/linux/slab.h:631:13: sparse: not a function <noident>
vim +2109 drivers/infiniband/hw/hns/hns_roce_hw_v1.c
9a443537 oulijun 2016-07-21 2005
d61d6de0 Bart Van Assche 2017-10-11 2006 static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
9a443537 oulijun 2016-07-21 2007 {
9a443537 oulijun 2016-07-21 2008 u32 doorbell[2];
9a443537 oulijun 2016-07-21 2009
9a443537 oulijun 2016-07-21 2010 doorbell[0] = cons_index & ((hr_cq->cq_depth << 1) - 1);
5b0ff9a0 Arnd Bergmann 2017-03-24 2011 doorbell[1] = 0;
9a443537 oulijun 2016-07-21 2012 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
9a443537 oulijun 2016-07-21 2013 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
9a443537 oulijun 2016-07-21 2014 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
9a443537 oulijun 2016-07-21 2015 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
9a443537 oulijun 2016-07-21 2016 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
9a443537 oulijun 2016-07-21 @2017 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
9a443537 oulijun 2016-07-21 2018 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
9a443537 oulijun 2016-07-21 2019
9a443537 oulijun 2016-07-21 @2020 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
9a443537 oulijun 2016-07-21 2021 }
9a443537 oulijun 2016-07-21 2022
9a443537 oulijun 2016-07-21 2023 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
9a443537 oulijun 2016-07-21 2024 struct hns_roce_srq *srq)
9a443537 oulijun 2016-07-21 2025 {
9a443537 oulijun 2016-07-21 2026 struct hns_roce_cqe *cqe, *dest;
9a443537 oulijun 2016-07-21 2027 u32 prod_index;
9a443537 oulijun 2016-07-21 2028 int nfreed = 0;
9a443537 oulijun 2016-07-21 2029 u8 owner_bit;
9a443537 oulijun 2016-07-21 2030
9a443537 oulijun 2016-07-21 2031 for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
9a443537 oulijun 2016-07-21 2032 ++prod_index) {
9a443537 oulijun 2016-07-21 2033 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
9a443537 oulijun 2016-07-21 2034 break;
9a443537 oulijun 2016-07-21 2035 }
9a443537 oulijun 2016-07-21 2036
9a443537 oulijun 2016-07-21 2037 /*
9a443537 oulijun 2016-07-21 2038 * Now backwards through the CQ, removing CQ entries
9a443537 oulijun 2016-07-21 2039 * that match our QP by overwriting them with next entries.
9a443537 oulijun 2016-07-21 2040 */
9a443537 oulijun 2016-07-21 2041 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
9a443537 oulijun 2016-07-21 2042 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
9a443537 oulijun 2016-07-21 2043 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
9a443537 oulijun 2016-07-21 2044 CQE_BYTE_16_LOCAL_QPN_S) &
9a443537 oulijun 2016-07-21 2045 HNS_ROCE_CQE_QPN_MASK) == qpn) {
9a443537 oulijun 2016-07-21 2046 /* In v1 engine, not support SRQ */
9a443537 oulijun 2016-07-21 2047 ++nfreed;
9a443537 oulijun 2016-07-21 2048 } else if (nfreed) {
9a443537 oulijun 2016-07-21 2049 dest = get_cqe(hr_cq, (prod_index + nfreed) &
9a443537 oulijun 2016-07-21 2050 hr_cq->ib_cq.cqe);
9a443537 oulijun 2016-07-21 2051 owner_bit = roce_get_bit(dest->cqe_byte_4,
9a443537 oulijun 2016-07-21 2052 CQE_BYTE_4_OWNER_S);
9a443537 oulijun 2016-07-21 2053 memcpy(dest, cqe, sizeof(*cqe));
9a443537 oulijun 2016-07-21 2054 roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
9a443537 oulijun 2016-07-21 2055 owner_bit);
9a443537 oulijun 2016-07-21 2056 }
9a443537 oulijun 2016-07-21 2057 }
9a443537 oulijun 2016-07-21 2058
9a443537 oulijun 2016-07-21 2059 if (nfreed) {
9a443537 oulijun 2016-07-21 2060 hr_cq->cons_index += nfreed;
9a443537 oulijun 2016-07-21 2061 /*
9a443537 oulijun 2016-07-21 2062 * Make sure update of buffer contents is done before
9a443537 oulijun 2016-07-21 2063 * updating consumer index.
9a443537 oulijun 2016-07-21 2064 */
9a443537 oulijun 2016-07-21 2065 wmb();
9a443537 oulijun 2016-07-21 2066
a4be892e Lijun Ou 2016-09-20 2067 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
9a443537 oulijun 2016-07-21 2068 }
9a443537 oulijun 2016-07-21 2069 }
9a443537 oulijun 2016-07-21 2070
9a443537 oulijun 2016-07-21 2071 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
9a443537 oulijun 2016-07-21 2072 struct hns_roce_srq *srq)
9a443537 oulijun 2016-07-21 2073 {
9a443537 oulijun 2016-07-21 2074 spin_lock_irq(&hr_cq->lock);
9a443537 oulijun 2016-07-21 2075 __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
9a443537 oulijun 2016-07-21 2076 spin_unlock_irq(&hr_cq->lock);
9a443537 oulijun 2016-07-21 2077 }
9a443537 oulijun 2016-07-21 2078
d61d6de0 Bart Van Assche 2017-10-11 2079 static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
d61d6de0 Bart Van Assche 2017-10-11 2080 struct hns_roce_cq *hr_cq, void *mb_buf,
d61d6de0 Bart Van Assche 2017-10-11 2081 u64 *mtts, dma_addr_t dma_handle, int nent,
d61d6de0 Bart Van Assche 2017-10-11 2082 u32 vector)
9a443537 oulijun 2016-07-21 2083 {
9a443537 oulijun 2016-07-21 2084 struct hns_roce_cq_context *cq_context = NULL;
8f3e9f3e Wei Hu (Xavier 2016-11-23 2085) struct hns_roce_buf_list *tptr_buf;
8f3e9f3e Wei Hu (Xavier 2016-11-23 2086) struct hns_roce_v1_priv *priv;
8f3e9f3e Wei Hu (Xavier 2016-11-23 2087) dma_addr_t tptr_dma_addr;
8f3e9f3e Wei Hu (Xavier 2016-11-23 2088) int offset;
8f3e9f3e Wei Hu (Xavier 2016-11-23 2089)
016a0059 Wei Hu(Xavier 2017-08-30 2090) priv = (struct hns_roce_v1_priv *)hr_dev->priv;
8f3e9f3e Wei Hu (Xavier 2016-11-23 2091) tptr_buf = &priv->tptr_table.tptr_buf;
9a443537 oulijun 2016-07-21 2092
9a443537 oulijun 2016-07-21 2093 cq_context = mb_buf;
9a443537 oulijun 2016-07-21 2094 memset(cq_context, 0, sizeof(*cq_context));
9a443537 oulijun 2016-07-21 2095
8f3e9f3e Wei Hu (Xavier 2016-11-23 2096) /* Get the tptr for this CQ. */
8f3e9f3e Wei Hu (Xavier 2016-11-23 2097) offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
8f3e9f3e Wei Hu (Xavier 2016-11-23 2098) tptr_dma_addr = tptr_buf->map + offset;
8f3e9f3e Wei Hu (Xavier 2016-11-23 2099) hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
9a443537 oulijun 2016-07-21 2100
9a443537 oulijun 2016-07-21 2101 /* Register cq_context members */
9a443537 oulijun 2016-07-21 2102 roce_set_field(cq_context->cqc_byte_4,
9a443537 oulijun 2016-07-21 2103 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
9a443537 oulijun 2016-07-21 2104 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
9a443537 oulijun 2016-07-21 2105 roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
9a443537 oulijun 2016-07-21 2106 CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
9a443537 oulijun 2016-07-21 2107 cq_context->cqc_byte_4 = cpu_to_le32(cq_context->cqc_byte_4);
9a443537 oulijun 2016-07-21 2108
9a443537 oulijun 2016-07-21 @2109 cq_context->cq_bt_l = (u32)dma_handle;
9a443537 oulijun 2016-07-21 2110 cq_context->cq_bt_l = cpu_to_le32(cq_context->cq_bt_l);
9a443537 oulijun 2016-07-21 2111
9a443537 oulijun 2016-07-21 2112 roce_set_field(cq_context->cqc_byte_12,
9a443537 oulijun 2016-07-21 2113 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
9a443537 oulijun 2016-07-21 2114 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
9a443537 oulijun 2016-07-21 2115 ((u64)dma_handle >> 32));
9a443537 oulijun 2016-07-21 2116 roce_set_field(cq_context->cqc_byte_12,
9a443537 oulijun 2016-07-21 2117 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
9a443537 oulijun 2016-07-21 2118 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
9a443537 oulijun 2016-07-21 2119 ilog2((unsigned int)nent));
9a443537 oulijun 2016-07-21 2120 roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
9a443537 oulijun 2016-07-21 2121 CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector);
9a443537 oulijun 2016-07-21 2122 cq_context->cqc_byte_12 = cpu_to_le32(cq_context->cqc_byte_12);
9a443537 oulijun 2016-07-21 2123
9a443537 oulijun 2016-07-21 @2124 cq_context->cur_cqe_ba0_l = (u32)(mtts[0]);
9a443537 oulijun 2016-07-21 2125 cq_context->cur_cqe_ba0_l = cpu_to_le32(cq_context->cur_cqe_ba0_l);
9a443537 oulijun 2016-07-21 2126
9a443537 oulijun 2016-07-21 2127 roce_set_field(cq_context->cqc_byte_20,
9a443537 oulijun 2016-07-21 2128 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
9a443537 oulijun 2016-07-21 2129 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S,
9a443537 oulijun 2016-07-21 2130 cpu_to_le32((mtts[0]) >> 32));
9a443537 oulijun 2016-07-21 2131 /* Dedicated hardware, directly set 0 */
9a443537 oulijun 2016-07-21 2132 roce_set_field(cq_context->cqc_byte_20,
9a443537 oulijun 2016-07-21 2133 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
9a443537 oulijun 2016-07-21 2134 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
9a443537 oulijun 2016-07-21 2135 /**
9a443537 oulijun 2016-07-21 2136 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
9a443537 oulijun 2016-07-21 2137 * using 4K page, and shift more 32 because of
9a443537 oulijun 2016-07-21 2138 * caculating the high 32 bit value evaluated to hardware.
9a443537 oulijun 2016-07-21 2139 */
9a443537 oulijun 2016-07-21 2140 roce_set_field(cq_context->cqc_byte_20,
9a443537 oulijun 2016-07-21 2141 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
9a443537 oulijun 2016-07-21 2142 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
8f3e9f3e Wei Hu (Xavier 2016-11-23 2143) tptr_dma_addr >> 44);
9a443537 oulijun 2016-07-21 2144 cq_context->cqc_byte_20 = cpu_to_le32(cq_context->cqc_byte_20);
9a443537 oulijun 2016-07-21 2145
8f3e9f3e Wei Hu (Xavier 2016-11-23 @2146) cq_context->cqe_tptr_addr_l = (u32)(tptr_dma_addr >> 12);
9a443537 oulijun 2016-07-21 2147
9a443537 oulijun 2016-07-21 2148 roce_set_field(cq_context->cqc_byte_32,
9a443537 oulijun 2016-07-21 2149 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
9a443537 oulijun 2016-07-21 2150 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
9a443537 oulijun 2016-07-21 2151 roce_set_bit(cq_context->cqc_byte_32,
9a443537 oulijun 2016-07-21 2152 CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
9a443537 oulijun 2016-07-21 2153 roce_set_bit(cq_context->cqc_byte_32,
9a443537 oulijun 2016-07-21 2154 CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
9a443537 oulijun 2016-07-21 2155 roce_set_bit(cq_context->cqc_byte_32,
9a443537 oulijun 2016-07-21 2156 CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
9a443537 oulijun 2016-07-21 2157 roce_set_bit(cq_context->cqc_byte_32,
9a443537 oulijun 2016-07-21 2158 CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
9a443537 oulijun 2016-07-21 2159 0);
9a443537 oulijun 2016-07-21 2160 /* The initial value of cq's ci is 0 */
9a443537 oulijun 2016-07-21 2161 roce_set_field(cq_context->cqc_byte_32,
9a443537 oulijun 2016-07-21 2162 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
9a443537 oulijun 2016-07-21 2163 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
9a443537 oulijun 2016-07-21 2164 cq_context->cqc_byte_32 = cpu_to_le32(cq_context->cqc_byte_32);
9a443537 oulijun 2016-07-21 2165 }
9a443537 oulijun 2016-07-21 2166
:::::: The code at line 2109 was first introduced by commit
:::::: 9a4435375cd151e07c0c38fa601b00115986091b IB/hns: Add driver files for hns RoCE driver
:::::: TO: oulijun <oulijun@huawei.com>
:::::: CC: Doug Ledford <dledford@redhat.com>
---
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在 2018/7/5 18:34, kbuild test robot 写道: > Hi Lijun, > > I love your patch! Perhaps something to improve: > > [auto build test WARNING on rdma/for-next] > [also build test WARNING on v4.18-rc3 next-20180704] > [cannot apply to linus/master linux-sof-driver/master] > [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] > > url: https://github.com/0day-ci/linux/commits/Lijun-Ou/Four-cmd-queues-support-and-sparse-checking/20180705-145936 > base: https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git for-next > reproduce: > # apt-get install sparse > make ARCH=x86_64 allmodconfig > make C=1 CF=-D__CHECK_ENDIAN__ > > > sparse warnings: (new ones prefixed by >>) > Hi，Jason I have used the sparse tool for checking and remove all warnings in my server. However, I don't know why? Thanks Lijun Ou > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1608:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1608:9: sparse: invalid assignment: |= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1608:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1608:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1705:9: sparse: invalid assignment: &= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1705:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1705:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1705:9: sparse: invalid assignment: |= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1705:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1705:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1707:9: sparse: invalid assignment: &= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1707:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1707:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1707:9: sparse: invalid assignment: |= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1707:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1707:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1709:9: sparse: invalid assignment: &= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1709:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1709:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1709:9: sparse: invalid assignment: |= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1709:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1709:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1710:9: sparse: invalid assignment: &= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1710:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1710:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1710:9: sparse: invalid assignment: |= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1710:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1710:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1711:9: sparse: invalid assignment: &= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1711:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1711:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1711:9: sparse: invalid assignment: |= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1711:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1711:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1743:18: sparse: cast to restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1743:18: sparse: cast from restricted __be32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1812:9: sparse: invalid assignment: &= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1812:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1812:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1812:9: sparse: invalid assignment: |= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1812:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1812:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1827:9: sparse: invalid assignment: &= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1827:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1827:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1827:9: sparse: invalid assignment: |= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1827:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1827:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1874:32: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] virt_addr_l @@ got unsignrestricted __le32 [usertype] virt_addr_l @@ > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1874:32: expected restricted __le32 [usertype] virt_addr_l > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1874:32: got unsigned int [unsigned] [usertype] <noident> > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1875:32: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] virt_addr_h @@ got unsignrestricted __le32 [usertype] virt_addr_h @@ > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1875:32: expected restricted __le32 [usertype] virt_addr_h > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1875:32: got unsigned int [unsigned] [usertype] <noident> > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1876:27: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] length @@ got unsignrestricted __le32 [usertype] length @@ > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1876:27: expected restricted __le32 [usertype] length > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1876:27: got unsigned int [unsigned] [usertype] <noident> > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1908:25: sparse: cast from restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1914:25: sparse: cast from restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1918:25: sparse: cast from restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1924:25: sparse: cast from restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1928:25: sparse: cast from restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1934:25: sparse: cast from restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1938:25: sparse: cast from restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1945:25: sparse: cast from restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1951:25: sparse: cast from restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1955:25: sparse: cast from restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1961:25: sparse: cast from restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1965:25: sparse: cast from restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1977:31: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] pbl_addr_l @@ got unsignrestricted __le32 [usertype] pbl_addr_l @@ > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1977:31: expected restricted __le32 [usertype] pbl_addr_l > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1977:31: got unsigned int [unsigned] [usertype] <noident> > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2012:9: sparse: invalid assignment: &= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2012:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2012:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2012:9: sparse: invalid assignment: |= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2012:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2012:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2013:9: sparse: invalid assignment: &= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2013:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2013:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2013:9: sparse: invalid assignment: |= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2013:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2013:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2015:9: sparse: invalid assignment: &= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2015:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2015:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2015:9: sparse: invalid assignment: |= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2015:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2015:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2017:9: sparse: invalid assignment: &= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2017:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2017:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2017:9: sparse: invalid assignment: |= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2017:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2017:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2020:28: sparse: incorrect type in argument 1 (different base types) @@ expected restricted __le32 [usertype] *val @@ got 2 [usertype] *val @@ > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2020:28: expected restricted __le32 [usertype] *val > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2020:28: got unsigned int *<noident> > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2107:34: sparse: cast from restricted __le32 >>> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2109:29: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] cq_bt_l @@ got unsignrestricted __le32 [usertype] cq_bt_l @@ > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2109:29: expected restricted __le32 [usertype] cq_bt_l > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2109:29: got unsigned int [unsigned] [usertype] <noident> > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2110:31: sparse: cast from restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2122:35: sparse: cast from restricted __le32 >>> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2124:35: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] cur_cqe_ba0_l @@ got unsignrestricted __le32 [usertype] cur_cqe_ba0_l @@ > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2124:35: expected restricted __le32 [usertype] cur_cqe_ba0_l > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2124:35: got unsigned int [unsigned] [usertype] <noident> > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2125:37: sparse: cast from restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2127:9: sparse: cast from restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2144:35: sparse: cast from restricted __le32 >>> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2146:37: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] cqe_tptr_addr_l @@ got unsignrestricted __le32 [usertype] cqe_tptr_addr_l @@ > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2146:37: expected restricted __le32 [usertype] cqe_tptr_addr_l > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2146:37: got unsigned int [unsigned] [usertype] <noident> > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2164:35: sparse: cast from restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2186:9: sparse: invalid assignment: &= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2186:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2186:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2186:9: sparse: invalid assignment: |= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2186:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2186:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2187:9: sparse: invalid assignment: &= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2187:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2187:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2187:9: sparse: invalid assignment: |= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2187:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2187:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2189:9: sparse: invalid assignment: &= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2189:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2189:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2189:9: sparse: invalid assignment: |= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2189:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2189:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2191:9: sparse: invalid assignment: &= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2191:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2191:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2191:9: sparse: invalid assignment: |= > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2191:9: left side has type unsigned int > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2191:9: right side has type restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2195:28: sparse: incorrect type in argument 1 (different base types) @@ expected restricted __le32 [usertype] *val @@ got 2 [usertype] *val @@ > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2195:28: expected restricted __le32 [usertype] *val > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2195:28: got unsigned int *<noident> > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2363:33: sparse: cast to restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2363:33: sparse: cast from restricted __be32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2363:33: sparse: cast to restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2363:33: sparse: cast from restricted __be32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2363:33: sparse: cast to restricted __le32 > drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2363:33: sparse: too many warnings > include/linux/slab.h:631:13: sparse: undefined identifier '__builtin_mul_overflow' > include/linux/slab.h:631:13: sparse: not a function <noident> > include/linux/slab.h:631:13: sparse: not a function <noident> > > vim +2109 drivers/infiniband/hw/hns/hns_roce_hw_v1.c > > 9a443537 oulijun 2016-07-21 2005 > d61d6de0 Bart Van Assche 2017-10-11 2006 static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index) > 9a443537 oulijun 2016-07-21 2007 { > 9a443537 oulijun 2016-07-21 2008 u32 doorbell[2]; > 9a443537 oulijun 2016-07-21 2009 > 9a443537 oulijun 2016-07-21 2010 doorbell[0] = cons_index & ((hr_cq->cq_depth << 1) - 1); > 5b0ff9a0 Arnd Bergmann 2017-03-24 2011 doorbell[1] = 0; > 9a443537 oulijun 2016-07-21 2012 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1); > 9a443537 oulijun 2016-07-21 2013 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M, > 9a443537 oulijun 2016-07-21 2014 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3); > 9a443537 oulijun 2016-07-21 2015 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M, > 9a443537 oulijun 2016-07-21 2016 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0); > 9a443537 oulijun 2016-07-21 @2017 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M, > 9a443537 oulijun 2016-07-21 2018 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn); > 9a443537 oulijun 2016-07-21 2019 > 9a443537 oulijun 2016-07-21 @2020 hns_roce_write64_k(doorbell, hr_cq->cq_db_l); > 9a443537 oulijun 2016-07-21 2021 } > 9a443537 oulijun 2016-07-21 2022 > 9a443537 oulijun 2016-07-21 2023 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, > 9a443537 oulijun 2016-07-21 2024 struct hns_roce_srq *srq) > 9a443537 oulijun 2016-07-21 2025 { > 9a443537 oulijun 2016-07-21 2026 struct hns_roce_cqe *cqe, *dest; > 9a443537 oulijun 2016-07-21 2027 u32 prod_index; > 9a443537 oulijun 2016-07-21 2028 int nfreed = 0; > 9a443537 oulijun 2016-07-21 2029 u8 owner_bit; > 9a443537 oulijun 2016-07-21 2030 > 9a443537 oulijun 2016-07-21 2031 for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index); > 9a443537 oulijun 2016-07-21 2032 ++prod_index) { > 9a443537 oulijun 2016-07-21 2033 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe) > 9a443537 oulijun 2016-07-21 2034 break; > 9a443537 oulijun 2016-07-21 2035 } > 9a443537 oulijun 2016-07-21 2036 > 9a443537 oulijun 2016-07-21 2037 /* > 9a443537 oulijun 2016-07-21 2038 * Now backwards through the CQ, removing CQ entries > 9a443537 oulijun 2016-07-21 2039 * that match our QP by overwriting them with next entries. > 9a443537 oulijun 2016-07-21 2040 */ > 9a443537 oulijun 2016-07-21 2041 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { > 9a443537 oulijun 2016-07-21 2042 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe); > 9a443537 oulijun 2016-07-21 2043 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M, > 9a443537 oulijun 2016-07-21 2044 CQE_BYTE_16_LOCAL_QPN_S) & > 9a443537 oulijun 2016-07-21 2045 HNS_ROCE_CQE_QPN_MASK) == qpn) { > 9a443537 oulijun 2016-07-21 2046 /* In v1 engine, not support SRQ */ > 9a443537 oulijun 2016-07-21 2047 ++nfreed; > 9a443537 oulijun 2016-07-21 2048 } else if (nfreed) { > 9a443537 oulijun 2016-07-21 2049 dest = get_cqe(hr_cq, (prod_index + nfreed) & > 9a443537 oulijun 2016-07-21 2050 hr_cq->ib_cq.cqe); > 9a443537 oulijun 2016-07-21 2051 owner_bit = roce_get_bit(dest->cqe_byte_4, > 9a443537 oulijun 2016-07-21 2052 CQE_BYTE_4_OWNER_S); > 9a443537 oulijun 2016-07-21 2053 memcpy(dest, cqe, sizeof(*cqe)); > 9a443537 oulijun 2016-07-21 2054 roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S, > 9a443537 oulijun 2016-07-21 2055 owner_bit); > 9a443537 oulijun 2016-07-21 2056 } > 9a443537 oulijun 2016-07-21 2057 } > 9a443537 oulijun 2016-07-21 2058 > 9a443537 oulijun 2016-07-21 2059 if (nfreed) { > 9a443537 oulijun 2016-07-21 2060 hr_cq->cons_index += nfreed; > 9a443537 oulijun 2016-07-21 2061 /* > 9a443537 oulijun 2016-07-21 2062 * Make sure update of buffer contents is done before > 9a443537 oulijun 2016-07-21 2063 * updating consumer index. > 9a443537 oulijun 2016-07-21 2064 */ > 9a443537 oulijun 2016-07-21 2065 wmb(); > 9a443537 oulijun 2016-07-21 2066 > a4be892e Lijun Ou 2016-09-20 2067 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index); > 9a443537 oulijun 2016-07-21 2068 } > 9a443537 oulijun 2016-07-21 2069 } > 9a443537 oulijun 2016-07-21 2070 > 9a443537 oulijun 2016-07-21 2071 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, > 9a443537 oulijun 2016-07-21 2072 struct hns_roce_srq *srq) > 9a443537 oulijun 2016-07-21 2073 { > 9a443537 oulijun 2016-07-21 2074 spin_lock_irq(&hr_cq->lock); > 9a443537 oulijun 2016-07-21 2075 __hns_roce_v1_cq_clean(hr_cq, qpn, srq); > 9a443537 oulijun 2016-07-21 2076 spin_unlock_irq(&hr_cq->lock); > 9a443537 oulijun 2016-07-21 2077 } > 9a443537 oulijun 2016-07-21 2078 > d61d6de0 Bart Van Assche 2017-10-11 2079 static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev, > d61d6de0 Bart Van Assche 2017-10-11 2080 struct hns_roce_cq *hr_cq, void *mb_buf, > d61d6de0 Bart Van Assche 2017-10-11 2081 u64 *mtts, dma_addr_t dma_handle, int nent, > d61d6de0 Bart Van Assche 2017-10-11 2082 u32 vector) > 9a443537 oulijun 2016-07-21 2083 { > 9a443537 oulijun 2016-07-21 2084 struct hns_roce_cq_context *cq_context = NULL; > 8f3e9f3e Wei Hu (Xavier 2016-11-23 2085) struct hns_roce_buf_list *tptr_buf; > 8f3e9f3e Wei Hu (Xavier 2016-11-23 2086) struct hns_roce_v1_priv *priv; > 8f3e9f3e Wei Hu (Xavier 2016-11-23 2087) dma_addr_t tptr_dma_addr; > 8f3e9f3e Wei Hu (Xavier 2016-11-23 2088) int offset; > 8f3e9f3e Wei Hu (Xavier 2016-11-23 2089) > 016a0059 Wei Hu(Xavier 2017-08-30 2090) priv = (struct hns_roce_v1_priv *)hr_dev->priv; > 8f3e9f3e Wei Hu (Xavier 2016-11-23 2091) tptr_buf = &priv->tptr_table.tptr_buf; > 9a443537 oulijun 2016-07-21 2092 > 9a443537 oulijun 2016-07-21 2093 cq_context = mb_buf; > 9a443537 oulijun 2016-07-21 2094 memset(cq_context, 0, sizeof(*cq_context)); > 9a443537 oulijun 2016-07-21 2095 > 8f3e9f3e Wei Hu (Xavier 2016-11-23 2096) /* Get the tptr for this CQ. */ > 8f3e9f3e Wei Hu (Xavier 2016-11-23 2097) offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE; > 8f3e9f3e Wei Hu (Xavier 2016-11-23 2098) tptr_dma_addr = tptr_buf->map + offset; > 8f3e9f3e Wei Hu (Xavier 2016-11-23 2099) hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset); > 9a443537 oulijun 2016-07-21 2100 > 9a443537 oulijun 2016-07-21 2101 /* Register cq_context members */ > 9a443537 oulijun 2016-07-21 2102 roce_set_field(cq_context->cqc_byte_4, > 9a443537 oulijun 2016-07-21 2103 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M, > 9a443537 oulijun 2016-07-21 2104 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID); > 9a443537 oulijun 2016-07-21 2105 roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M, > 9a443537 oulijun 2016-07-21 2106 CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn); > 9a443537 oulijun 2016-07-21 2107 cq_context->cqc_byte_4 = cpu_to_le32(cq_context->cqc_byte_4); > 9a443537 oulijun 2016-07-21 2108 > 9a443537 oulijun 2016-07-21 @2109 cq_context->cq_bt_l = (u32)dma_handle; > 9a443537 oulijun 2016-07-21 2110 cq_context->cq_bt_l = cpu_to_le32(cq_context->cq_bt_l); > 9a443537 oulijun 2016-07-21 2111 > 9a443537 oulijun 2016-07-21 2112 roce_set_field(cq_context->cqc_byte_12, > 9a443537 oulijun 2016-07-21 2113 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M, > 9a443537 oulijun 2016-07-21 2114 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S, > 9a443537 oulijun 2016-07-21 2115 ((u64)dma_handle >> 32)); > 9a443537 oulijun 2016-07-21 2116 roce_set_field(cq_context->cqc_byte_12, > 9a443537 oulijun 2016-07-21 2117 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M, > 9a443537 oulijun 2016-07-21 2118 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S, > 9a443537 oulijun 2016-07-21 2119 ilog2((unsigned int)nent)); > 9a443537 oulijun 2016-07-21 2120 roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M, > 9a443537 oulijun 2016-07-21 2121 CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector); > 9a443537 oulijun 2016-07-21 2122 cq_context->cqc_byte_12 = cpu_to_le32(cq_context->cqc_byte_12); > 9a443537 oulijun 2016-07-21 2123 > 9a443537 oulijun 2016-07-21 @2124 cq_context->cur_cqe_ba0_l = (u32)(mtts[0]); > 9a443537 oulijun 2016-07-21 2125 cq_context->cur_cqe_ba0_l = cpu_to_le32(cq_context->cur_cqe_ba0_l); > 9a443537 oulijun 2016-07-21 2126 > 9a443537 oulijun 2016-07-21 2127 roce_set_field(cq_context->cqc_byte_20, > 9a443537 oulijun 2016-07-21 2128 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M, > 9a443537 oulijun 2016-07-21 2129 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S, > 9a443537 oulijun 2016-07-21 2130 cpu_to_le32((mtts[0]) >> 32)); > 9a443537 oulijun 2016-07-21 2131 /* Dedicated hardware, directly set 0 */ > 9a443537 oulijun 2016-07-21 2132 roce_set_field(cq_context->cqc_byte_20, > 9a443537 oulijun 2016-07-21 2133 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M, > 9a443537 oulijun 2016-07-21 2134 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0); > 9a443537 oulijun 2016-07-21 2135 /** > 9a443537 oulijun 2016-07-21 2136 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of > 9a443537 oulijun 2016-07-21 2137 * using 4K page, and shift more 32 because of > 9a443537 oulijun 2016-07-21 2138 * caculating the high 32 bit value evaluated to hardware. > 9a443537 oulijun 2016-07-21 2139 */ > 9a443537 oulijun 2016-07-21 2140 roce_set_field(cq_context->cqc_byte_20, > 9a443537 oulijun 2016-07-21 2141 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M, > 9a443537 oulijun 2016-07-21 2142 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S, > 8f3e9f3e Wei Hu (Xavier 2016-11-23 2143) tptr_dma_addr >> 44); > 9a443537 oulijun 2016-07-21 2144 cq_context->cqc_byte_20 = cpu_to_le32(cq_context->cqc_byte_20); > 9a443537 oulijun 2016-07-21 2145 > 8f3e9f3e Wei Hu (Xavier 2016-11-23 @2146) cq_context->cqe_tptr_addr_l = (u32)(tptr_dma_addr >> 12); > 9a443537 oulijun 2016-07-21 2147 > 9a443537 oulijun 2016-07-21 2148 roce_set_field(cq_context->cqc_byte_32, > 9a443537 oulijun 2016-07-21 2149 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M, > 9a443537 oulijun 2016-07-21 2150 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0); > 9a443537 oulijun 2016-07-21 2151 roce_set_bit(cq_context->cqc_byte_32, > 9a443537 oulijun 2016-07-21 2152 CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0); > 9a443537 oulijun 2016-07-21 2153 roce_set_bit(cq_context->cqc_byte_32, > 9a443537 oulijun 2016-07-21 2154 CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0); > 9a443537 oulijun 2016-07-21 2155 roce_set_bit(cq_context->cqc_byte_32, > 9a443537 oulijun 2016-07-21 2156 CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0); > 9a443537 oulijun 2016-07-21 2157 roce_set_bit(cq_context->cqc_byte_32, > 9a443537 oulijun 2016-07-21 2158 CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S, > 9a443537 oulijun 2016-07-21 2159 0); > 9a443537 oulijun 2016-07-21 2160 /* The initial value of cq's ci is 0 */ > 9a443537 oulijun 2016-07-21 2161 roce_set_field(cq_context->cqc_byte_32, > 9a443537 oulijun 2016-07-21 2162 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M, > 9a443537 oulijun 2016-07-21 2163 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0); > 9a443537 oulijun 2016-07-21 2164 cq_context->cqc_byte_32 = cpu_to_le32(cq_context->cqc_byte_32); > 9a443537 oulijun 2016-07-21 2165 } > 9a443537 oulijun 2016-07-21 2166 > > :::::: The code at line 2109 was first introduced by commit > :::::: 9a4435375cd151e07c0c38fa601b00115986091b IB/hns: Add driver files for hns RoCE driver > > :::::: TO: oulijun <oulijun@huawei.com> > :::::: CC: Doug Ledford <dledford@redhat.com> > > --- > 0-DAY kernel test infrastructure Open Source Technology Center > https://lists.01.org/pipermail/kbuild-all Intel Corporation > > . > -- To unsubscribe from this list: send the line "unsubscribe linux-rdma" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Jul 05, 2018 at 07:02:52PM +0800, oulijun wrote: > 在 2018/7/5 18:34, kbuild test robot 写道: > > Hi Lijun, > > > > I love your patch! Perhaps something to improve: > > > > [auto build test WARNING on rdma/for-next] > > [also build test WARNING on v4.18-rc3 next-20180704] > > [cannot apply to linus/master linux-sof-driver/master] > > [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] > > > > url: https://github.com/0day-ci/linux/commits/Lijun-Ou/Four-cmd-queues-support-and-sparse-checking/20180705-145936 > > base: https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git for-next > > reproduce: > > # apt-get install sparse > > make ARCH=x86_64 allmodconfig > > make C=1 CF=-D__CHECK_ENDIAN__ > > > > > > sparse warnings: (new ones prefixed by >>) > > > Hi，Jason > I have used the sparse tool for checking and remove all warnings > in my server. However, I don't know why? I don't know what is wrong with your setup, you have to figure it out. Make sure you are running a sufficiently new version of sparse as a first step, and follow the build steps given above. Jason -- To unsubscribe from this list: send the line "unsubscribe linux-rdma" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h index 65f7b68..c8101bd 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -864,7 +864,7 @@ static inline struct hns_roce_sqp *hr_to_hr_sqp(struct hns_roce_qp *hr_qp) return container_of(hr_qp, struct hns_roce_sqp, hr_qp); } -static inline void hns_roce_write64_k(__be32 val[2], void __iomem *dest) +static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) { __raw_writeq(*(u64 *) val, dest); } diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c index 235c67d..0dedef6 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c @@ -175,10 +175,10 @@ static int hns_roce_v1_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, UD_SEND_WQE_U32_36_FLOW_LABEL_M, UD_SEND_WQE_U32_36_FLOW_LABEL_S, 0); roce_set_field(ud_sq_wqe->u32_36, - UD_SEND_WQE_U32_36_PRIORITY_M, - UD_SEND_WQE_U32_36_PRIORITY_S, - ah->av.sl_tclass_flowlabel >> - HNS_ROCE_SL_SHIFT); + UD_SEND_WQE_U32_36_PRIORITY_M, + UD_SEND_WQE_U32_36_PRIORITY_S, + le32_to_cpu(ah->av.sl_tclass_flowlabel) >> + HNS_ROCE_SL_SHIFT); roce_set_field(ud_sq_wqe->u32_36, UD_SEND_WQE_U32_36_SGID_INDEX_M, UD_SEND_WQE_U32_36_SGID_INDEX_S, @@ -333,7 +333,7 @@ static int hns_roce_v1_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, doorbell[0] = le32_to_cpu(sq_db.u32_4); doorbell[1] = le32_to_cpu(sq_db.u32_8); - hns_roce_write64_k(doorbell, qp->sq.db_reg_l); + hns_roce_write64_k((__le32 *)doorbell, qp->sq.db_reg_l); qp->sq_next_wqe = ind; } @@ -349,7 +349,7 @@ static int hns_roce_v1_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, int nreq = 0; int ind = 0; int i = 0; - u32 reg_val = 0; + u32 reg_val; unsigned long flags = 0; struct hns_roce_rq_wqe_ctrl *ctrl = NULL; struct hns_roce_wqe_data_seg *scat = NULL; @@ -402,14 +402,18 @@ static int hns_roce_v1_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, wmb(); if (ibqp->qp_type == IB_QPT_GSI) { + __le32 tmp; + /* SW update GSI rq header */ reg_val = roce_read(to_hr_dev(ibqp->device), ROCEE_QP1C_CFG3_0_REG + QP1C_CFGN_OFFSET * hr_qp->phy_port); - roce_set_field(reg_val, + tmp = cpu_to_le32(reg_val); + roce_set_field(tmp, ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M, ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S, hr_qp->rq.head); + reg_val = le32_to_cpu(tmp); roce_write(to_hr_dev(ibqp->device), ROCEE_QP1C_CFG3_0_REG + QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val); @@ -430,7 +434,8 @@ static int hns_roce_v1_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, doorbell[0] = le32_to_cpu(rq_db.u32_4); doorbell[1] = le32_to_cpu(rq_db.u32_8); - hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l); + hns_roce_write64_k((__le32 *)doorbell, + hr_qp->rq.db_reg_l); } } spin_unlock_irqrestore(&hr_qp->rq.lock, flags); @@ -441,51 +446,63 @@ static int hns_roce_v1_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev, int sdb_mode, int odb_mode) { + __le32 tmp; u32 val; val = roce_read(hr_dev, ROCEE_GLB_CFG_REG); - roce_set_bit(val, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode); - roce_set_bit(val, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode); + tmp = cpu_to_le32(val); + roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode); + roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode); + val = le32_to_cpu(tmp); roce_write(hr_dev, ROCEE_GLB_CFG_REG, val); } static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode, u32 odb_mode) { + __le32 tmp; u32 val; /* Configure SDB/ODB extend mode */ val = roce_read(hr_dev, ROCEE_GLB_CFG_REG); - roce_set_bit(val, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode); - roce_set_bit(val, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode); + tmp = cpu_to_le32(val); + roce_set_bit(tmp, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode); + roce_set_bit(tmp, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode); + val = le32_to_cpu(tmp); roce_write(hr_dev, ROCEE_GLB_CFG_REG, val); } static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept, u32 sdb_alful) { + __le32 tmp; u32 val; /* Configure SDB */ val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG); - roce_set_field(val, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M, + tmp = cpu_to_le32(val); + roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful); - roce_set_field(val, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M, + roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept); + val = le32_to_cpu(tmp); roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val); } static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept, u32 odb_alful) { + __le32 tmp; u32 val; /* Configure ODB */ val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG); - roce_set_field(val, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M, + tmp = cpu_to_le32(val); + roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful); - roce_set_field(val, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M, + roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept); + val = le32_to_cpu(tmp); roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val); } @@ -496,6 +513,7 @@ static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept, struct hns_roce_v1_priv *priv; struct hns_roce_db_table *db; dma_addr_t sdb_dma_addr; + __le32 tmp; u32 val; priv = (struct hns_roce_v1_priv *)hr_dev->priv; @@ -511,7 +529,8 @@ static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept, /* Configure extend SDB depth */ val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG); - roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M, + tmp = cpu_to_le32(val); + roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S, db->ext_db->esdb_dep); /* @@ -519,8 +538,9 @@ static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept, * using 4K page, and shift more 32 because of * caculating the high 32 bit value evaluated to hardware. */ - roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M, + roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44); + val = le32_to_cpu(tmp); roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val); dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep); @@ -535,6 +555,7 @@ static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept, struct hns_roce_v1_priv *priv; struct hns_roce_db_table *db; dma_addr_t odb_dma_addr; + __le32 tmp; u32 val; priv = (struct hns_roce_v1_priv *)hr_dev->priv; @@ -550,12 +571,14 @@ static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept, /* Configure extend ODB depth */ val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG); - roce_set_field(val, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M, + tmp = cpu_to_le32(val); + roce_set_field(tmp, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S, db->ext_db->eodb_dep); - roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M, + roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S, db->ext_db->eodb_dep); + val = le32_to_cpu(tmp); roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val); dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
This patch removes the warnings by sparse tool checking. Signed-off-by: Lijun Ou <oulijun@huawei.com> --- drivers/infiniband/hw/hns/hns_roce_device.h | 2 +- drivers/infiniband/hw/hns/hns_roce_hw_v1.c | 63 ++++++++++++++++++++--------- 2 files changed, 44 insertions(+), 21 deletions(-)