| Message ID | 20180703123214.23090-7-paul@crapouillou.net (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
On 3 July 2018 at 18:02, Paul Cercueil <paul@crapouillou.net> wrote: > The JZ4725B has one DMA core starring six DMA channels. > As for the JZ4770, each DMA channel's clock can be enabled with > a register write, the difference here being that once started, it > is not possible to turn it off. > > Signed-off-by: Paul Cercueil <paul@crapouillou.net> > --- > Documentation/devicetree/bindings/dma/jz4780-dma.txt | 1 + > drivers/dma/dma-jz4780.c | 6 ++++++ > 2 files changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/dma/jz4780-dma.txt b/Documentation/devicetree/bindings/dma/jz4780-dma.txt > index d7ca3f925fdf..5d302b488e88 100644 > --- a/Documentation/devicetree/bindings/dma/jz4780-dma.txt > +++ b/Documentation/devicetree/bindings/dma/jz4780-dma.txt > @@ -5,6 +5,7 @@ Required properties: > - compatible: Should be one of: > * ingenic,jz4780-dma > * ingenic,jz4770-dma > + * ingenic,jz4725b-dma > * ingenic,jz4740-dma > - reg: Should contain the DMA channel registers location and length, followed > by the DMA controller registers location and length. > diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c > index ccadbe61dde7..922e4031e70e 100644 > --- a/drivers/dma/dma-jz4780.c > +++ b/drivers/dma/dma-jz4780.c > @@ -134,6 +134,7 @@ struct jz4780_dma_chan { > > enum jz_version { > ID_JZ4740, > + ID_JZ4725B, > ID_JZ4770, > ID_JZ4780, > }; > @@ -204,6 +205,8 @@ static inline void jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma, > { > if (jzdma->version == ID_JZ4770) > jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKES, BIT(chn)); > + else if (jzdma->version == ID_JZ4725B) > + jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKE, BIT(chn)); > } > > static inline void jz4780_dma_chan_disable(struct jz4780_dma_dev *jzdma, > @@ -249,6 +252,7 @@ static void jz4780_dma_desc_free(struct virt_dma_desc *vdesc) > > static const unsigned int jz4780_dma_ord_max[] = { > [ID_JZ4740] = 5, > + [ID_JZ4725B] = 5, > [ID_JZ4770] = 6, > [ID_JZ4780] = 7, > }; > @@ -804,12 +808,14 @@ static struct dma_chan *jz4780_of_dma_xlate(struct of_phandle_args *dma_spec, > > static const unsigned int jz4780_dma_nb_channels[] = { > [ID_JZ4740] = 6, > + [ID_JZ4725B] = 6, > [ID_JZ4770] = 6, > [ID_JZ4780] = 32, > }; > > static const struct of_device_id jz4780_dma_dt_match[] = { > { .compatible = "ingenic,jz4740-dma", .data = (void *)ID_JZ4740 }, > + { .compatible = "ingenic,jz4725b-dma", .data = (void *)ID_JZ4725B }, > { .compatible = "ingenic,jz4770-dma", .data = (void *)ID_JZ4770 }, > { .compatible = "ingenic,jz4780-dma", .data = (void *)ID_JZ4780 }, > {}, > -- > 2.18.0 > > Reviewed-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 03-07-18, 14:32, Paul Cercueil wrote: > The JZ4725B has one DMA core starring six DMA channels. > As for the JZ4770, each DMA channel's clock can be enabled with > a register write, the difference here being that once started, it > is not possible to turn it off. ok so disable for this, right.. > @@ -204,6 +205,8 @@ static inline void jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma, > { > if (jzdma->version == ID_JZ4770) > jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKES, BIT(chn)); > + else if (jzdma->version == ID_JZ4725B) > + jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKE, BIT(chn)); but you are writing to a different register here..
Le lun. 9 juil. 2018 à 19:14, Vinod <vkoul@kernel.org> a écrit : > On 03-07-18, 14:32, Paul Cercueil wrote: >> The JZ4725B has one DMA core starring six DMA channels. >> As for the JZ4770, each DMA channel's clock can be enabled with >> a register write, the difference here being that once started, it >> is not possible to turn it off. > > ok so disable for this, right.. > >> @@ -204,6 +205,8 @@ static inline void >> jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma, >> { >> if (jzdma->version == ID_JZ4770) >> jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKES, BIT(chn)); >> + else if (jzdma->version == ID_JZ4725B) >> + jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKE, BIT(chn)); > > but you are writing to a different register here.. Yes. SoCs >= JZ4770 have the DCKE read-only register, and DCKES/DCKEC to set/clear bits in DCKE. On JZ4725B, DCKE is read/write, but the zeros written are ignored (at least that's what the documentation says). > -- > ~Vinod Thanks, -Paul -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 10-07-18, 17:45, Paul Cercueil wrote: > > > Le lun. 9 juil. 2018 à 19:14, Vinod <vkoul@kernel.org> a écrit : > > On 03-07-18, 14:32, Paul Cercueil wrote: > > > The JZ4725B has one DMA core starring six DMA channels. > > > As for the JZ4770, each DMA channel's clock can be enabled with > > > a register write, the difference here being that once started, it > > > is not possible to turn it off. > > > > ok so disable for this, right.. > > > > > @@ -204,6 +205,8 @@ static inline void > > > jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma, > > > { > > > if (jzdma->version == ID_JZ4770) > > > jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKES, BIT(chn)); > > > + else if (jzdma->version == ID_JZ4725B) > > > + jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKE, BIT(chn)); > > > > but you are writing to a different register here.. > > Yes. SoCs >= JZ4770 have the DCKE read-only register, and DCKES/DCKEC to > set/clear bits in DCKE. > On JZ4725B, DCKE is read/write, but the zeros written are ignored (at least > that's what the > documentation says). and that was not documented in the log... so i though it maybe a typo.
Le mer. 11 juil. 2018 à 14:18, Vinod <vkoul@kernel.org> a écrit : > On 10-07-18, 17:45, Paul Cercueil wrote: >> >> >> Le lun. 9 juil. 2018 à 19:14, Vinod <vkoul@kernel.org> a écrit : >> > On 03-07-18, 14:32, Paul Cercueil wrote: >> > > The JZ4725B has one DMA core starring six DMA channels. >> > > As for the JZ4770, each DMA channel's clock can be enabled with >> > > a register write, the difference here being that once started, >> it >> > > is not possible to turn it off. >> > >> > ok so disable for this, right.. >> > >> > > @@ -204,6 +205,8 @@ static inline void >> > > jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma, >> > > { >> > > if (jzdma->version == ID_JZ4770) >> > > jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKES, BIT(chn)); >> > > + else if (jzdma->version == ID_JZ4725B) >> > > + jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKE, BIT(chn)); >> > >> > but you are writing to a different register here.. >> >> Yes. SoCs >= JZ4770 have the DCKE read-only register, and >> DCKES/DCKEC to >> set/clear bits in DCKE. >> On JZ4725B, DCKE is read/write, but the zeros written are ignored >> (at least >> that's what the >> documentation says). > > and that was not documented in the log... so i though it maybe a typo. Right, I will add a comment in-code to explain that it's normal. > -- > ~Vinod Thanks, -Paul -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/dma/jz4780-dma.txt b/Documentation/devicetree/bindings/dma/jz4780-dma.txt index d7ca3f925fdf..5d302b488e88 100644 --- a/Documentation/devicetree/bindings/dma/jz4780-dma.txt +++ b/Documentation/devicetree/bindings/dma/jz4780-dma.txt @@ -5,6 +5,7 @@ Required properties: - compatible: Should be one of: * ingenic,jz4780-dma * ingenic,jz4770-dma + * ingenic,jz4725b-dma * ingenic,jz4740-dma - reg: Should contain the DMA channel registers location and length, followed by the DMA controller registers location and length. diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c index ccadbe61dde7..922e4031e70e 100644 --- a/drivers/dma/dma-jz4780.c +++ b/drivers/dma/dma-jz4780.c @@ -134,6 +134,7 @@ struct jz4780_dma_chan { enum jz_version { ID_JZ4740, + ID_JZ4725B, ID_JZ4770, ID_JZ4780, }; @@ -204,6 +205,8 @@ static inline void jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma, { if (jzdma->version == ID_JZ4770) jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKES, BIT(chn)); + else if (jzdma->version == ID_JZ4725B) + jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKE, BIT(chn)); } static inline void jz4780_dma_chan_disable(struct jz4780_dma_dev *jzdma, @@ -249,6 +252,7 @@ static void jz4780_dma_desc_free(struct virt_dma_desc *vdesc) static const unsigned int jz4780_dma_ord_max[] = { [ID_JZ4740] = 5, + [ID_JZ4725B] = 5, [ID_JZ4770] = 6, [ID_JZ4780] = 7, }; @@ -804,12 +808,14 @@ static struct dma_chan *jz4780_of_dma_xlate(struct of_phandle_args *dma_spec, static const unsigned int jz4780_dma_nb_channels[] = { [ID_JZ4740] = 6, + [ID_JZ4725B] = 6, [ID_JZ4770] = 6, [ID_JZ4780] = 32, }; static const struct of_device_id jz4780_dma_dt_match[] = { { .compatible = "ingenic,jz4740-dma", .data = (void *)ID_JZ4740 }, + { .compatible = "ingenic,jz4725b-dma", .data = (void *)ID_JZ4725B }, { .compatible = "ingenic,jz4770-dma", .data = (void *)ID_JZ4770 }, { .compatible = "ingenic,jz4780-dma", .data = (void *)ID_JZ4780 }, {},
The JZ4725B has one DMA core starring six DMA channels. As for the JZ4770, each DMA channel's clock can be enabled with a register write, the difference here being that once started, it is not possible to turn it off. Signed-off-by: Paul Cercueil <paul@crapouillou.net> --- Documentation/devicetree/bindings/dma/jz4780-dma.txt | 1 + drivers/dma/dma-jz4780.c | 6 ++++++ 2 files changed, 7 insertions(+)