| Message ID | 87527531b135f4eb7fb51d4e7ee82723cd162a6c.1531753039.git.ryder.lee@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 16/07/18 16:59, Ryder Lee wrote: > The input clock of UART0 should be CLK_PERI_UART0_PD. > > Fixes: 13f36c326cef ("arm64: dts: mt7622: turn uart0 clock to real ones") > Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> > --- pused to v4.18-next/dts64 Thanks a lot! > change since v1: > - add Fixes tag. > --- > arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi > index 8cdec52..4caa9b4 100644 > --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi > @@ -367,7 +367,7 @@ > reg = <0 0x11002000 0 0x400>; > interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; > clocks = <&topckgen CLK_TOP_UART_SEL>, > - <&pericfg CLK_PERI_UART1_PD>; > + <&pericfg CLK_PERI_UART0_PD>; > clock-names = "baud", "bus"; > status = "disabled"; > }; >
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 8cdec52..4caa9b4 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -367,7 +367,7 @@ reg = <0 0x11002000 0 0x400>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART1_PD>; + <&pericfg CLK_PERI_UART0_PD>; clock-names = "baud", "bus"; status = "disabled"; };
The input clock of UART0 should be CLK_PERI_UART0_PD. Fixes: 13f36c326cef ("arm64: dts: mt7622: turn uart0 clock to real ones") Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> --- change since v1: - add Fixes tag. --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)