| Message ID | 1532630184-29450-6-git-send-email-arun.parameswaran@broadcom.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add clock config and pm support to bcm iProc mdio mux | expand |
> @@ -175,6 +198,12 @@ static int mdio_mux_iproc_probe(struct platform_device *pdev) > return PTR_ERR(md->base); > } > > + md->core_clk = devm_clk_get(&pdev->dev, NULL); > + if (IS_ERR(md->core_clk)) { > + dev_info(&pdev->dev, "core_clk not specified\n"); > + md->core_clk = NULL; > + } > + In the binding, you say the clock is optional. This is a rather strong message for something which is optional. I think it would be better to not output anything. Andrew
On 18-07-26 12:13 PM, Andrew Lunn wrote: >> @@ -175,6 +198,12 @@ static int mdio_mux_iproc_probe(struct platform_device *pdev) >> return PTR_ERR(md->base); >> } >> >> + md->core_clk = devm_clk_get(&pdev->dev, NULL); >> + if (IS_ERR(md->core_clk)) { >> + dev_info(&pdev->dev, "core_clk not specified\n"); >> + md->core_clk = NULL; >> + } >> + > > In the binding, you say the clock is optional. This is a rather strong > message for something which is optional. I think it would be better to > not output anything. > > Andrew > Will remove the message. Thanks Arun
> +static void mdio_mux_iproc_config_clk(struct iproc_mdiomux_desc *md) > +{ > + u32 val; > + u32 divisor; > + > + if (md->core_clk) { > + divisor = clk_get_rate(md->core_clk) / MDIO_OPERATING_FREQUENCY; /** * clk_get_rate - obtain the current clock rate (in Hz) for a clock source. * This is only valid once the clock source has been enabled. * @clk: clock source */ unsigned long clk_get_rate(struct clk *clk); It is generally good practice to call clk_prepare_enable() sometime before clk_get_rate() to ensure the clock is ticking, and to show this driver is making use of the clock, so it does not get turned off. > + divisor = divisor / (MDIO_RATE_ADJ_DIVIDENT + 1); > + val = divisor; > + val |= MDIO_RATE_ADJ_DIVIDENT << MDIO_RATE_ADJ_DIVIDENT_SHIFT; > + writel(val, md->base + MDIO_RATE_ADJ_EXT_OFFSET); > + writel(val, md->base + MDIO_RATE_ADJ_INT_OFFSET); > + } > +}
Hi Andrew On 18-07-26 12:26 PM, Andrew Lunn wrote: >> +static void mdio_mux_iproc_config_clk(struct iproc_mdiomux_desc *md) >> +{ >> + u32 val; >> + u32 divisor; >> + >> + if (md->core_clk) { >> + divisor = clk_get_rate(md->core_clk) / MDIO_OPERATING_FREQUENCY; > > /** > * clk_get_rate - obtain the current clock rate (in Hz) for a clock source. > * This is only valid once the clock source has been enabled. > * @clk: clock source > */ > unsigned long clk_get_rate(struct clk *clk); > > It is generally good practice to call clk_prepare_enable() sometime > before clk_get_rate() to ensure the clock is ticking, and to show this > driver is making use of the clock, so it does not get turned off. Will add 'clk_prepare_enable()' to the probe. Thanks Arun > >> + divisor = divisor / (MDIO_RATE_ADJ_DIVIDENT + 1); >> + val = divisor; >> + val |= MDIO_RATE_ADJ_DIVIDENT << MDIO_RATE_ADJ_DIVIDENT_SHIFT; >> + writel(val, md->base + MDIO_RATE_ADJ_EXT_OFFSET); >> + writel(val, md->base + MDIO_RATE_ADJ_INT_OFFSET); >> + } >> +}
diff --git a/drivers/net/phy/mdio-mux-bcm-iproc.c b/drivers/net/phy/mdio-mux-bcm-iproc.c index dc65e95..6b400dd 100644 --- a/drivers/net/phy/mdio-mux-bcm-iproc.c +++ b/drivers/net/phy/mdio-mux-bcm-iproc.c @@ -13,7 +13,7 @@ * You should have received a copy of the GNU General Public License * version 2 (GPLv2) along with this source code. */ - +#include <linux/clk.h> #include <linux/platform_device.h> #include <linux/device.h> #include <linux/of_mdio.h> @@ -22,6 +22,10 @@ #include <linux/mdio-mux.h> #include <linux/delay.h> +#define MDIO_RATE_ADJ_EXT_OFFSET 0x000 +#define MDIO_RATE_ADJ_INT_OFFSET 0x004 +#define MDIO_RATE_ADJ_DIVIDENT_SHIFT 16 + #define MDIO_PARAM_OFFSET 0x23c #define MDIO_PARAM_MIIM_CYCLE 29 #define MDIO_PARAM_INTERNAL_SEL 25 @@ -44,13 +48,32 @@ #define BUS_MAX_ADDR 32 #define EXT_BUS_START_ADDR 16 +#define MDIO_OPERATING_FREQUENCY 11000000 +#define MDIO_RATE_ADJ_DIVIDENT 1 + struct iproc_mdiomux_desc { void *mux_handle; void __iomem *base; struct device *dev; struct mii_bus *mii_bus; + struct clk *core_clk; }; +static void mdio_mux_iproc_config_clk(struct iproc_mdiomux_desc *md) +{ + u32 val; + u32 divisor; + + if (md->core_clk) { + divisor = clk_get_rate(md->core_clk) / MDIO_OPERATING_FREQUENCY; + divisor = divisor / (MDIO_RATE_ADJ_DIVIDENT + 1); + val = divisor; + val |= MDIO_RATE_ADJ_DIVIDENT << MDIO_RATE_ADJ_DIVIDENT_SHIFT; + writel(val, md->base + MDIO_RATE_ADJ_EXT_OFFSET); + writel(val, md->base + MDIO_RATE_ADJ_INT_OFFSET); + } +} + static int iproc_mdio_wait_for_idle(void __iomem *base, bool result) { unsigned int timeout = 1000; /* loop for 1s */ @@ -175,6 +198,12 @@ static int mdio_mux_iproc_probe(struct platform_device *pdev) return PTR_ERR(md->base); } + md->core_clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(md->core_clk)) { + dev_info(&pdev->dev, "core_clk not specified\n"); + md->core_clk = NULL; + } + md->mii_bus = mdiobus_alloc(); if (!md->mii_bus) { dev_err(&pdev->dev, "mdiomux bus alloc failed\n"); @@ -206,6 +235,8 @@ static int mdio_mux_iproc_probe(struct platform_device *pdev) goto out_register; } + mdio_mux_iproc_config_clk(md); + dev_info(md->dev, "iProc mdiomux registered\n"); return 0;
Add support to configure the internal rate adjust register based on the core clock supplied through device tree in the Broadcom iProc mdio mux. The operating frequency of the mdio mux block is 11MHz. This is derrived by dividing the clock to the mdio mux with the rate adjust register. In some SoC's the default values of the rate adjust register do not yield 11MHz. These SoC's are required to specify the clock via the device tree for proper operation. Signed-off-by: Arun Parameswaran <arun.parameswaran@broadcom.com> --- drivers/net/phy/mdio-mux-bcm-iproc.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-)