| Message ID | 1533374735-16662-5-git-send-email-manish.narani@xilinx.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | EDAC: Enhancements to Synopsys EDAC driver | expand |
Ping. > -----Original Message----- > From: Manish Narani [mailto:manish.narani@xilinx.com] > Sent: Saturday, August 4, 2018 2:56 PM > To: robh+dt@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com; > will.deacon@arm.com; Michal Simek <michals@xilinx.com>; bp@alien8.de; > mchehab@kernel.org; mdf@kernel.org; Edgar Iglesias <edgari@xilinx.com>; > Shubhrajyoti Datta <shubhraj@xilinx.com>; Naga Sureshkumar Relli > <nagasure@xilinx.com>; Bharat Kumar Gogada <bharatku@xilinx.com>; > stefan.krsmanovic@aggios.com > Cc: Srinivas Goud <sgoud@xilinx.com>; Anirudha Sarangi > <anirudh@xilinx.com>; linux-kernel@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > edac@vger.kernel.org; Manish Narani <MNARANI@xilinx.com> > Subject: [PATCH v4 4/4] arm64: zynqmp: Add DDRC node > > This patch adds ddrc memory controller node in dts. The size mentioned in dts > is 0x30000, because we need to access DDR_QOS INTR registers located at > fd090208 from this driver. > > Signed-off-by: Manish Narani <manish.narani@xilinx.com> > --- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index a091e6f..7d6a3cf 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -355,6 +355,13 @@ > xlnx,bus-width = <64>; > }; > > + mc: memory-controller@fd070000 { > + compatible = "xlnx,zynqmp-ddrc-2.40a"; > + reg = <0x0 0xfd070000 0x0 0x30000>; > + interrupt-parent = <&gic>; > + interrupts = <0 112 4>; > + }; > + > gem0: ethernet@ff0b0000 { > compatible = "cdns,zynqmp-gem", "cdns,gem"; > status = "disabled"; > -- > 2.1.1
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index a091e6f..7d6a3cf 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -355,6 +355,13 @@ xlnx,bus-width = <64>; }; + mc: memory-controller@fd070000 { + compatible = "xlnx,zynqmp-ddrc-2.40a"; + reg = <0x0 0xfd070000 0x0 0x30000>; + interrupt-parent = <&gic>; + interrupts = <0 112 4>; + }; + gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled";
This patch adds ddrc memory controller node in dts. The size mentioned in dts is 0x30000, because we need to access DDR_QOS INTR registers located at fd090208 from this driver. Signed-off-by: Manish Narani <manish.narani@xilinx.com> --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)