diff mbox series

[v2,2/2] drm/msm/dpu: fix for cursor blend issue

Message ID 20180822174957.22684-3-skolluku@codeaurora.org (mailing list archive)
State New, archived
Headers show
Series Enable cursor plane on DPU | expand

Commit Message

Sravanthi Kollukuduru Aug. 22, 2018, 5:49 p.m. UTC
The current driver has the opaque blend mode set as the
default causing the black box effect around the cursor.
The fix enables choosing a different blend mode for alpha
enabled formats.

Changes in V2:
	- Use drm_get_format_name() in the logs (Sean)

Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 26 +++++++++++++++++++++-----
 1 file changed, 21 insertions(+), 5 deletions(-)

Comments

Sean Paul Aug. 22, 2018, 7:11 p.m. UTC | #1
On Wed, Aug 22, 2018 at 11:19:57PM +0530, Sravanthi Kollukuduru wrote:
> The current driver has the opaque blend mode set as the
> default causing the black box effect around the cursor.
> The fix enables choosing a different blend mode for alpha
> enabled formats.
> 
> Changes in V2:
> 	- Use drm_get_format_name() in the logs (Sean)
> 
> Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org>

Reviewed-by: Sean Paul <seanpaul@chromium.org>

I've applied this to dpu-staging/for-next.

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 26 +++++++++++++++++++++-----
>  1 file changed, 21 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 0cd9456a6c4c..07c2d15b45f2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -297,14 +297,29 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
>  }
>  
>  static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
> -		struct dpu_plane_state *pstate)
> +		struct dpu_plane_state *pstate, struct dpu_format *format)
>  {
>  	struct dpu_hw_mixer *lm = mixer->hw_lm;
> +	uint32_t blend_op;
> +	struct drm_format_name_buf format_name;
>  
>  	/* default to opaque blending */
> -	lm->ops.setup_blend_config(lm, pstate->stage, 0XFF, 0,
> -				DPU_BLEND_FG_ALPHA_FG_CONST |
> -				DPU_BLEND_BG_ALPHA_BG_CONST);
> +	blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
> +		DPU_BLEND_BG_ALPHA_BG_CONST;
> +
> +	if (format->alpha_enable) {
> +		/* coverage blending */
> +		blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
> +			DPU_BLEND_BG_ALPHA_FG_PIXEL |
> +			DPU_BLEND_BG_INV_ALPHA;
> +	}
> +
> +	lm->ops.setup_blend_config(lm, pstate->stage,
> +				0xFF, 0, blend_op);
> +
> +	DPU_DEBUG("format:%s, alpha_en:%u blend_op:0x%x\n",
> +		drm_get_format_name(format->base.pixel_format, &format_name),
> +		format->alpha_enable, blend_op);
>  }
>  
>  static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
> @@ -401,7 +416,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
>  
>  		/* blend config update */
>  		for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
> -			_dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate);
> +			_dpu_crtc_setup_blend_cfg(mixer + lm_idx,
> +						pstate, format);
>  
>  			mixer[lm_idx].flush_mask |= flush_mask;
>  
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 0cd9456a6c4c..07c2d15b45f2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -297,14 +297,29 @@  static void dpu_crtc_destroy(struct drm_crtc *crtc)
 }
 
 static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
-		struct dpu_plane_state *pstate)
+		struct dpu_plane_state *pstate, struct dpu_format *format)
 {
 	struct dpu_hw_mixer *lm = mixer->hw_lm;
+	uint32_t blend_op;
+	struct drm_format_name_buf format_name;
 
 	/* default to opaque blending */
-	lm->ops.setup_blend_config(lm, pstate->stage, 0XFF, 0,
-				DPU_BLEND_FG_ALPHA_FG_CONST |
-				DPU_BLEND_BG_ALPHA_BG_CONST);
+	blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
+		DPU_BLEND_BG_ALPHA_BG_CONST;
+
+	if (format->alpha_enable) {
+		/* coverage blending */
+		blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
+			DPU_BLEND_BG_ALPHA_FG_PIXEL |
+			DPU_BLEND_BG_INV_ALPHA;
+	}
+
+	lm->ops.setup_blend_config(lm, pstate->stage,
+				0xFF, 0, blend_op);
+
+	DPU_DEBUG("format:%s, alpha_en:%u blend_op:0x%x\n",
+		drm_get_format_name(format->base.pixel_format, &format_name),
+		format->alpha_enable, blend_op);
 }
 
 static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
@@ -401,7 +416,8 @@  static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
 
 		/* blend config update */
 		for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
-			_dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate);
+			_dpu_crtc_setup_blend_cfg(mixer + lm_idx,
+						pstate, format);
 
 			mixer[lm_idx].flush_mask |= flush_mask;