| Message ID | d5574b7b-9bb6-1f24-f2b4-2036c66a2924@cogentembedded.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | mmc: renesas_sdhi_internal_dmac: fix #define RST_RESERVED_BITS | expand |
On Wed, Aug 22, 2018 at 09:28:01PM +0300, Sergei Shtylyov wrote: > The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits > 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Suggesting stable.
On 08/22/2018 10:38 PM, Wolfram Sang wrote: >> The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits >> 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS. >> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > > Suggesting stable. Stable looks at the Fixes: tags now. Should I add that? MBR, Sergei
On Wed, Aug 22, 2018 at 10:41:56PM +0300, Sergei Shtylyov wrote: > On 08/22/2018 10:38 PM, Wolfram Sang wrote: > > >> The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits > >> 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS. > >> > >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > > > Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > > > > Suggesting stable. > > Stable looks at the Fixes: tags now. Should I add that? Yes, that would be great IMHO.
On 08/22/2018 10:45 PM, Wolfram Sang wrote: >>>> The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits >>>> 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS. >>>> >>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> >>> >>> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> >>> >>> Suggesting stable. >> >> Stable looks at the Fixes: tags now. Should I add that? > > Yes, that would be great IMHO. Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC") Hopefully, Ulf uses patchwork. :-) MBR, Sergei
On 22 August 2018 at 22:03, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > On 08/22/2018 10:45 PM, Wolfram Sang wrote: > >>>>> The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits >>>>> 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS. >>>>> >>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> >>>> >>>> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> >>>> >>>> Suggesting stable. >>> >>> Stable looks at the Fixes: tags now. Should I add that? >> >> Yes, that would be great IMHO. > > Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC") > > Hopefully, Ulf uses patchwork. :-) I do. However, fixes tags doesn't seem to get picked up. Anyway, it's easy for me to add them. Applied for fixes, thanks! Kind regards Uffe
On 08/23/2018 01:43 PM, Ulf Hansson wrote: >>>>>> The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits >>>>>> 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS. >>>>>> >>>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> >>>>> >>>>> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> >>>>> >>>>> Suggesting stable. >>>> >>>> Stable looks at the Fixes: tags now. Should I add that? >>> >>> Yes, that would be great IMHO. >> >> Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC") >> >> Hopefully, Ulf uses patchwork. :-) > > I do. However, fixes tags doesn't seem to get picked up. Anyway, it's I figured after writing... only patchwork.ozlabs.org seems to pick those up. > easy for me to add them. > > Applied for fixes, thanks! Thank you! > Kind regards > Uffe MBR, Sergei
Index: mmc/drivers/mmc/host/renesas_sdhi_internal_dmac.c =================================================================== --- mmc.orig/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ mmc/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -45,7 +45,7 @@ /* DM_CM_RST */ #define RST_DTRANRST1 BIT(9) #define RST_DTRANRST0 BIT(8) -#define RST_RESERVED_BITS GENMASK_ULL(32, 0) +#define RST_RESERVED_BITS GENMASK_ULL(31, 0) /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ #define INFO1_CLEAR 0
The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- The patch is against Ulf Hansson's 'mmc.git' repo's 'fixes' branch. drivers/mmc/host/renesas_sdhi_internal_dmac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)