diff mbox series

[v2,1/5] drm/vc4: Fix TILE_Y_OFFSET definitions

Message ID 20180803092231.26446-1-boris.brezillon@bootlin.com (mailing list archive)
State New, archived
Headers show
Series [v2,1/5] drm/vc4: Fix TILE_Y_OFFSET definitions | expand

Commit Message

Boris Brezillon Aug. 3, 2018, 9:22 a.m. UTC 
From: Eric Anholt <eric@anholt.net>

Y_OFFSET field starts at bit 8 not 7.

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
---
Changes in v2:
- None
---
 drivers/gpu/drm/vc4/vc4_regs.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Eric Anholt Aug. 6, 2018, 8:02 p.m. UTC | #1 
Boris Brezillon <boris.brezillon@bootlin.com> writes:

> From: Eric Anholt <eric@anholt.net>
>
> Y_OFFSET field starts at bit 8 not 7.
>
> Signed-off-by: Eric Anholt <eric@anholt.net>
> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>

Your changes in this series have my r-b.  Time to add your ack to my
changes in this series and push?
Boris Brezillon Aug. 6, 2018, 8:12 p.m. UTC | #2 
On Mon, 06 Aug 2018 13:02:48 -0700
Eric Anholt <eric@anholt.net> wrote:

> Boris Brezillon <boris.brezillon@bootlin.com> writes:
> 
> > From: Eric Anholt <eric@anholt.net>
> >
> > Y_OFFSET field starts at bit 8 not 7.
> >
> > Signed-off-by: Eric Anholt <eric@anholt.net>
> > Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>  
> 
> Your changes in this series have my r-b.  Time to add your ack to my

Adding SoB implicitly means A-b for me, but I can add them if you
prefer. 

> changes in this series and push?

Sure, I was just waiting for your green light after the changes I've
done in patch 3.
Eric Anholt Aug. 7, 2018, 12:41 a.m. UTC | #3 
Boris Brezillon <boris.brezillon@bootlin.com> writes:

> On Mon, 06 Aug 2018 13:02:48 -0700
> Eric Anholt <eric@anholt.net> wrote:
>
>> Boris Brezillon <boris.brezillon@bootlin.com> writes:
>> 
>> > From: Eric Anholt <eric@anholt.net>
>> >
>> > Y_OFFSET field starts at bit 8 not 7.
>> >
>> > Signed-off-by: Eric Anholt <eric@anholt.net>
>> > Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>  
>> 
>> Your changes in this series have my r-b.  Time to add your ack to my
>
> Adding SoB implicitly means A-b for me, but I can add them if you
> prefer. 

Yeah, I guess that does, you're right.
Boris Brezillon Aug. 24, 2018, 7:09 a.m. UTC | #4 
On Fri,  3 Aug 2018 11:22:27 +0200
Boris Brezillon <boris.brezillon@bootlin.com> wrote:

> From: Eric Anholt <eric@anholt.net>
> 
> Y_OFFSET field starts at bit 8 not 7.
> 
> Signed-off-by: Eric Anholt <eric@anholt.net>
> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>

As discussed with Eric 2 weeks ago, I'm about to apply this series to
drm-misc-fixes. The rational behind this decision is that those patches
are actually fixing the driver, even though they don't all have Fixes
and Cc-stable tags.

Daniel, any objection?

> ---
> Changes in v2:
> - None
> ---
>  drivers/gpu/drm/vc4/vc4_regs.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
> index d6864fa4bd14..ccbd6b377ffe 100644
> --- a/drivers/gpu/drm/vc4/vc4_regs.h
> +++ b/drivers/gpu/drm/vc4/vc4_regs.h
> @@ -1043,8 +1043,8 @@ enum hvs_pixel_format {
>  #define SCALER_PITCH0_TILE_LINE_DIR		BIT(15)
>  #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR	BIT(14)
>  /* Y offset within a tile. */
> -#define SCALER_PITCH0_TILE_Y_OFFSET_MASK	VC4_MASK(13, 7)
> -#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT	7
> +#define SCALER_PITCH0_TILE_Y_OFFSET_MASK	VC4_MASK(13, 8)
> +#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT	8
>  #define SCALER_PITCH0_TILE_WIDTH_R_MASK		VC4_MASK(6, 0)
>  #define SCALER_PITCH0_TILE_WIDTH_R_SHIFT	0
>
Boris Brezillon Aug. 24, 2018, 7:42 a.m. UTC | #5 
On Fri, 24 Aug 2018 09:09:26 +0200
Boris Brezillon <boris.brezillon@bootlin.com> wrote:

> On Fri,  3 Aug 2018 11:22:27 +0200
> Boris Brezillon <boris.brezillon@bootlin.com> wrote:
> 
> > From: Eric Anholt <eric@anholt.net>
> > 
> > Y_OFFSET field starts at bit 8 not 7.
> > 
> > Signed-off-by: Eric Anholt <eric@anholt.net>
> > Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>  
> 
> As discussed with Eric 2 weeks ago, I'm about to apply this series to
> drm-misc-fixes. The rational behind this decision is that those patches
> are actually fixing the driver, even though they don't all have Fixes
> and Cc-stable tags.
> 
> Daniel, any objection?

Actually it conflicts in a few places because this series was based on
drm-misc-next, so I'll wait for 4.19-rc1 to be back-merged in
drm-misc-fixes before applying the patchset.

> 
> > ---
> > Changes in v2:
> > - None
> > ---
> >  drivers/gpu/drm/vc4/vc4_regs.h | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
> > index d6864fa4bd14..ccbd6b377ffe 100644
> > --- a/drivers/gpu/drm/vc4/vc4_regs.h
> > +++ b/drivers/gpu/drm/vc4/vc4_regs.h
> > @@ -1043,8 +1043,8 @@ enum hvs_pixel_format {
> >  #define SCALER_PITCH0_TILE_LINE_DIR		BIT(15)
> >  #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR	BIT(14)
> >  /* Y offset within a tile. */
> > -#define SCALER_PITCH0_TILE_Y_OFFSET_MASK	VC4_MASK(13, 7)
> > -#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT	7
> > +#define SCALER_PITCH0_TILE_Y_OFFSET_MASK	VC4_MASK(13, 8)
> > +#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT	8
> >  #define SCALER_PITCH0_TILE_WIDTH_R_MASK		VC4_MASK(6, 0)
> >  #define SCALER_PITCH0_TILE_WIDTH_R_SHIFT	0
> >    
>
Boris Brezillon Aug. 27, 2018, 7:09 p.m. UTC | #6 
On Fri,  3 Aug 2018 11:22:27 +0200
Boris Brezillon <boris.brezillon@bootlin.com> wrote:

> From: Eric Anholt <eric@anholt.net>
> 
> Y_OFFSET field starts at bit 8 not 7.
> 
> Signed-off-by: Eric Anholt <eric@anholt.net>
> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>

Queued the series to drm-misc-fixes.

> ---
> Changes in v2:
> - None
> ---
>  drivers/gpu/drm/vc4/vc4_regs.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
> index d6864fa4bd14..ccbd6b377ffe 100644
> --- a/drivers/gpu/drm/vc4/vc4_regs.h
> +++ b/drivers/gpu/drm/vc4/vc4_regs.h
> @@ -1043,8 +1043,8 @@ enum hvs_pixel_format {
>  #define SCALER_PITCH0_TILE_LINE_DIR		BIT(15)
>  #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR	BIT(14)
>  /* Y offset within a tile. */
> -#define SCALER_PITCH0_TILE_Y_OFFSET_MASK	VC4_MASK(13, 7)
> -#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT	7
> +#define SCALER_PITCH0_TILE_Y_OFFSET_MASK	VC4_MASK(13, 8)
> +#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT	8
>  #define SCALER_PITCH0_TILE_WIDTH_R_MASK		VC4_MASK(6, 0)
>  #define SCALER_PITCH0_TILE_WIDTH_R_SHIFT	0
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index d6864fa4bd14..ccbd6b377ffe 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -1043,8 +1043,8 @@  enum hvs_pixel_format {
 #define SCALER_PITCH0_TILE_LINE_DIR		BIT(15)
 #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR	BIT(14)
 /* Y offset within a tile. */
-#define SCALER_PITCH0_TILE_Y_OFFSET_MASK	VC4_MASK(13, 7)
-#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT	7
+#define SCALER_PITCH0_TILE_Y_OFFSET_MASK	VC4_MASK(13, 8)
+#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT	8
 #define SCALER_PITCH0_TILE_WIDTH_R_MASK		VC4_MASK(6, 0)
 #define SCALER_PITCH0_TILE_WIDTH_R_SHIFT	0