| Message ID | 1535453838-12154-11-git-send-email-sunil.kovvuri@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | soc: octeontx2: Add RVU admin function driver | expand |
On Tue, Aug 28, 2018 at 12:58 PM <sunil.kovvuri@gmail.com> wrote: > > From: Geetha sowjanya <gakula@marvell.com> > > HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence > create a IOMMU mapping for the physcial address configured by > firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. > > Signed-off-by: Geetha sowjanya <gakula@marvell.com> > Signed-off-by: Sunil Goutham <sgoutham@marvell.com> I think this needs some more explanation. What is the difference between the MSI-X support in this driver and every other one? Are you working around a hardware bug, or is there something odd in the implementation of your irqchip driver? Do you use a GIC to handle the MSI interrupts or something else? Arnd
On Tue, Aug 28, 2018 at 5:39 PM Arnd Bergmann <arnd@arndb.de> wrote: > > On Tue, Aug 28, 2018 at 12:58 PM <sunil.kovvuri@gmail.com> wrote: > > > > From: Geetha sowjanya <gakula@marvell.com> > > > > HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence > > create a IOMMU mapping for the physcial address configured by > > firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. > > > > Signed-off-by: Geetha sowjanya <gakula@marvell.com> > > Signed-off-by: Sunil Goutham <sgoutham@marvell.com> > > I think this needs some more explanation. What is the difference between > the MSI-X support in this driver and every other one? Are you working > around a hardware bug, or is there something odd in the implementation > of your irqchip driver? Do you use a GIC to handle the MSI interrupts > or something else? > > Arnd This admin function is a PCI device which is capable of provisioning HW blocks to other PCIe SRIOV devices in the system. Each HW block (eg memory buffer pools, NIC dewscriptors, crypto engines e.t.c) needs certain no of MSIX vectors. Admin function has a set of 32K MSIX vectors in memory (not on-chip) which based on HW block provisioning to a PCI device attaches the required number of vectors to that device. Some part of this configuration is done by low level firmware. RVU_AF_MSIXTR_BASE points to the memory region allocated for 32K MSIX vectors. If kernel is booted with IOMMU enabled and admin function device is attached to SMMU, HW will go through translation to access this MSIX vector memory region. Hence the mapping done in this patch. Thanks, Sunil.
On Tue, Aug 28, 2018 at 2:42 PM Sunil Kovvuri <sunil.kovvuri@gmail.com> wrote: > > On Tue, Aug 28, 2018 at 5:39 PM Arnd Bergmann <arnd@arndb.de> wrote: > > > > On Tue, Aug 28, 2018 at 12:58 PM <sunil.kovvuri@gmail.com> wrote: > > > > > > From: Geetha sowjanya <gakula@marvell.com> > > > > > > HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence > > > create a IOMMU mapping for the physcial address configured by > > > firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. > > > > > > Signed-off-by: Geetha sowjanya <gakula@marvell.com> > > > Signed-off-by: Sunil Goutham <sgoutham@marvell.com> > > > > I think this needs some more explanation. What is the difference between > > the MSI-X support in this driver and every other one? Are you working > > around a hardware bug, or is there something odd in the implementation > > of your irqchip driver? Do you use a GIC to handle the MSI interrupts > > or something else? > > This admin function is a PCI device which is capable of provisioning > HW blocks to other PCIe SRIOV devices in the system. Each HW block > (eg memory buffer pools, NIC dewscriptors, crypto engines e.t.c) needs > certain no of MSIX vectors. Admin function has a set of 32K MSIX vectors > in memory (not on-chip) which based on HW block provisioning to a PCI device > attaches the required number of vectors to that device. Some part of this > configuration is done by low level firmware. > > RVU_AF_MSIXTR_BASE points to the memory region allocated for 32K MSIX > vectors. If kernel is booted with IOMMU enabled and admin function device > is attached to SMMU, HW will go through translation to access this MSIX > vector memory region. Hence the mapping done in this patch. Do you mean this is not a regular PCIe MSI-X interrupt to the GIC, but something internal to your device that gets routed through the IOMMU back into the device? I'm still confused. Arnd
On Tue, Aug 28, 2018 at 6:27 PM Arnd Bergmann <arnd@arndb.de> wrote: > > On Tue, Aug 28, 2018 at 2:42 PM Sunil Kovvuri <sunil.kovvuri@gmail.com> wrote: > > > > On Tue, Aug 28, 2018 at 5:39 PM Arnd Bergmann <arnd@arndb.de> wrote: > > > > > > On Tue, Aug 28, 2018 at 12:58 PM <sunil.kovvuri@gmail.com> wrote: > > > > > > > > From: Geetha sowjanya <gakula@marvell.com> > > > > > > > > HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence > > > > create a IOMMU mapping for the physcial address configured by > > > > firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. > > > > > > > > Signed-off-by: Geetha sowjanya <gakula@marvell.com> > > > > Signed-off-by: Sunil Goutham <sgoutham@marvell.com> > > > > > > I think this needs some more explanation. What is the difference between > > > the MSI-X support in this driver and every other one? Are you working > > > around a hardware bug, or is there something odd in the implementation > > > of your irqchip driver? Do you use a GIC to handle the MSI interrupts > > > or something else? > > > > This admin function is a PCI device which is capable of provisioning > > HW blocks to other PCIe SRIOV devices in the system. Each HW block > > (eg memory buffer pools, NIC dewscriptors, crypto engines e.t.c) needs > > certain no of MSIX vectors. Admin function has a set of 32K MSIX vectors > > in memory (not on-chip) which based on HW block provisioning to a PCI device > > attaches the required number of vectors to that device. Some part of this > > configuration is done by low level firmware. > > > > RVU_AF_MSIXTR_BASE points to the memory region allocated for 32K MSIX > > vectors. If kernel is booted with IOMMU enabled and admin function device > > is attached to SMMU, HW will go through translation to access this MSIX > > vector memory region. Hence the mapping done in this patch. > > Do you mean this is not a regular PCIe MSI-X interrupt to the GIC, but > something internal to your device that gets routed through the IOMMU > back into the device? > > I'm still confused. > > Arnd This is a regular PCIe MSI-X interrupt, the difference is that the bunch of PCI devices here doesn't have a fixed set of MSIX vectors. Admin function has a memory region with 32K MSIX vectors which it provisions to PCI devices based on the HW functional blocks attached to them. A PCI device which works as a ethernet device needs X number of vectors and a crypto device needs Y number of vectors. Since the admin function owns the whole MSIX vector region, HW uses this device's stream ID to access the vectors. Hence the IOMMU mapping. Once MSIX vectors are provisioned to a PCI device they work as normal MSIX interrupt like any other device. Thanks, Sunil.
On Tue, Aug 28, 2018 at 3:17 PM Sunil Kovvuri <sunil.kovvuri@gmail.com> wrote: > On Tue, Aug 28, 2018 at 6:27 PM Arnd Bergmann <arnd@arndb.de> wrote: > > On Tue, Aug 28, 2018 at 2:42 PM Sunil Kovvuri <sunil.kovvuri@gmail.com> wrote: > > > On Tue, Aug 28, 2018 at 5:39 PM Arnd Bergmann <arnd@arndb.de> wrote: > > > > On Tue, Aug 28, 2018 at 12:58 PM <sunil.kovvuri@gmail.com> wrote: > > > > > > This admin function is a PCI device which is capable of provisioning > > > HW blocks to other PCIe SRIOV devices in the system. Each HW block > > > (eg memory buffer pools, NIC dewscriptors, crypto engines e.t.c) needs > > > certain no of MSIX vectors. Admin function has a set of 32K MSIX vectors > > > in memory (not on-chip) which based on HW block provisioning to a PCI device > > > attaches the required number of vectors to that device. Some part of this > > > configuration is done by low level firmware. > > > > > > RVU_AF_MSIXTR_BASE points to the memory region allocated for 32K MSIX > > > vectors. If kernel is booted with IOMMU enabled and admin function device > > > is attached to SMMU, HW will go through translation to access this MSIX > > > vector memory region. Hence the mapping done in this patch. > > > > Do you mean this is not a regular PCIe MSI-X interrupt to the GIC, but > > something internal to your device that gets routed through the IOMMU > > back into the device? > > > > This is a regular PCIe MSI-X interrupt, the difference is that the > bunch of PCI devices > here doesn't have a fixed set of MSIX vectors. Admin function has a > memory region with > 32K MSIX vectors which it provisions to PCI devices based on the HW > functional blocks > attached to them. A PCI device which works as a ethernet device needs > X number of vectors > and a crypto device needs Y number of vectors. > > Since the admin function owns the whole MSIX vector region, HW uses > this device's stream ID > to access the vectors. Hence the IOMMU mapping. Once MSIX vectors are > provisioned to > a PCI device they work as normal MSIX interrupt like any other device. Ok, I think I got it now, just to confirm: the MSIX vectors you allocate in the admin device refer to memory backing the BAR that contains the MSI-X entries of the other functions, right? I was a bit confused here and assumed that you were mapping the MMIO area of an interrupt controller that receives the interupt transactions. Arnd
On Thu, Aug 30, 2018 at 7:23 PM Arnd Bergmann <arnd@arndb.de> wrote: > > On Tue, Aug 28, 2018 at 3:17 PM Sunil Kovvuri <sunil.kovvuri@gmail.com> wrote: > > On Tue, Aug 28, 2018 at 6:27 PM Arnd Bergmann <arnd@arndb.de> wrote: > > > On Tue, Aug 28, 2018 at 2:42 PM Sunil Kovvuri <sunil.kovvuri@gmail.com> wrote: > > > > On Tue, Aug 28, 2018 at 5:39 PM Arnd Bergmann <arnd@arndb.de> wrote: > > > > > On Tue, Aug 28, 2018 at 12:58 PM <sunil.kovvuri@gmail.com> wrote: > > > > > > > > This admin function is a PCI device which is capable of provisioning > > > > HW blocks to other PCIe SRIOV devices in the system. Each HW block > > > > (eg memory buffer pools, NIC dewscriptors, crypto engines e.t.c) needs > > > > certain no of MSIX vectors. Admin function has a set of 32K MSIX vectors > > > > in memory (not on-chip) which based on HW block provisioning to a PCI device > > > > attaches the required number of vectors to that device. Some part of this > > > > configuration is done by low level firmware. > > > > > > > > RVU_AF_MSIXTR_BASE points to the memory region allocated for 32K MSIX > > > > vectors. If kernel is booted with IOMMU enabled and admin function device > > > > is attached to SMMU, HW will go through translation to access this MSIX > > > > vector memory region. Hence the mapping done in this patch. > > > > > > Do you mean this is not a regular PCIe MSI-X interrupt to the GIC, but > > > something internal to your device that gets routed through the IOMMU > > > back into the device? > > > > > > > This is a regular PCIe MSI-X interrupt, the difference is that the > > bunch of PCI devices > > here doesn't have a fixed set of MSIX vectors. Admin function has a > > memory region with > > 32K MSIX vectors which it provisions to PCI devices based on the HW > > functional blocks > > attached to them. A PCI device which works as a ethernet device needs > > X number of vectors > > and a crypto device needs Y number of vectors. > > > > Since the admin function owns the whole MSIX vector region, HW uses > > this device's stream ID > > to access the vectors. Hence the IOMMU mapping. Once MSIX vectors are > > provisioned to > > a PCI device they work as normal MSIX interrupt like any other device. > > Ok, I think I got it now, just to confirm: the MSIX vectors you allocate > in the admin device refer to memory backing the BAR that contains > the MSI-X entries of the other functions, right? Yes, that's correct. > > I was a bit confused here and assumed that you were mapping > the MMIO area of an interrupt controller that receives the interupt > transactions. > > Arnd
diff --git a/drivers/soc/marvell/octeontx2/rvu.c b/drivers/soc/marvell/octeontx2/rvu.c index 8ac3524..40684c9 100644 --- a/drivers/soc/marvell/octeontx2/rvu.c +++ b/drivers/soc/marvell/octeontx2/rvu.c @@ -442,9 +442,10 @@ static int rvu_setup_msix_resources(struct rvu *rvu) { struct rvu_hwinfo *hw = rvu->hw; int pf, vf, numvfs, hwvf, err; + int nvecs, offset, max_msix; struct rvu_pfvf *pfvf; - int nvecs, offset; - u64 cfg; + u64 cfg, phy_addr; + dma_addr_t iova; for (pf = 0; pf < hw->total_pfs; pf++) { cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); @@ -523,6 +524,22 @@ static int rvu_setup_msix_resources(struct rvu *rvu) } } + /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence + * create a IOMMU mapping for the physcial address configured by + * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. + */ + cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); + max_msix = cfg & 0xFFFFF; + phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE); + iova = dma_map_single(rvu->dev, (void *)phy_addr, + max_msix * PCI_MSIX_ENTRY_SIZE, + DMA_BIDIRECTIONAL); + if (dma_mapping_error(rvu->dev, iova)) + return -ENOMEM; + + rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); + rvu->msix_base_iova = iova; + return 0; } @@ -531,7 +548,8 @@ static void rvu_free_hw_resources(struct rvu *rvu) struct rvu_hwinfo *hw = rvu->hw; struct rvu_block *block; struct rvu_pfvf *pfvf; - int id; + int id, max_msix; + u64 cfg; /* Free block LF bitmaps */ for (id = 0; id < BLK_COUNT; id++) { @@ -549,6 +567,15 @@ static void rvu_free_hw_resources(struct rvu *rvu) pfvf = &rvu->hwvf[id]; kfree(pfvf->msix.bmap); } + + /* Unmap MSIX vector base IOVA mapping */ + if (!rvu->msix_base_iova) + return; + cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); + max_msix = cfg & 0xFFFFF; + dma_unmap_single(rvu->dev, rvu->msix_base_iova, + max_msix * PCI_MSIX_ENTRY_SIZE, + DMA_BIDIRECTIONAL); } static int rvu_setup_hw_resources(struct rvu *rvu) diff --git a/drivers/soc/marvell/octeontx2/rvu.h b/drivers/soc/marvell/octeontx2/rvu.h index 7435e83..92c2022 100644 --- a/drivers/soc/marvell/octeontx2/rvu.h +++ b/drivers/soc/marvell/octeontx2/rvu.h @@ -99,6 +99,7 @@ struct rvu { u16 num_vec; char *irq_name; bool *irq_allocated; + dma_addr_t msix_base_iova; }; static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)