| Message ID | 20180912131641.21688-1-m.szyprowski@samsung.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend | expand |
On 09/12/2018 03:16 PM, Marek Szyprowski wrote: > All sclk_uart clocks in TOP CMU have to be kept enabled for suspend/resume > cycle, otherwise TM2(e) boards hangs before entering the suspend mode. > > Signed-off-by: Marek Szyprowski<m.szyprowski@samsung.com> Patch applied, thanks.
On 09/12/2018 03:16 PM, Marek Szyprowski wrote: > All sclk_uart clocks in TOP CMU have to be kept enabled for suspend/resume > cycle, otherwise TM2(e) boards hangs before entering the suspend mode. > > Signed-off-by: Marek Szyprowski<m.szyprowski@samsung.com> Patch applied, thanks.
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 13384f4911c7..84eac0ce5682 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -180,6 +180,8 @@ static const unsigned long top_clk_regs[] __initconst = { static const struct samsung_clk_reg_dump top_suspend_regs[] = { /* force all aclk clocks enabled */ { ENABLE_ACLK_TOP, 0x67ecffed }, + /* force all sclk_uart clocks enabled */ + { ENABLE_SCLK_TOP_PERIC, 0x38 }, /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ { ISP_PLL_CON0, 0x85cc0502 }, /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
All sclk_uart clocks in TOP CMU have to be kept enabled for suspend/resume cycle, otherwise TM2(e) boards hangs before entering the suspend mode. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> --- This change was missing in the initial patch, because 'no_console_suspend' kernel option did almost the same. --- drivers/clk/samsung/clk-exynos5433.c | 2 ++ 1 file changed, 2 insertions(+)