| Message ID | 20180917163103.6113-35-cota@braap.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | exec: drop BQL from interrupt handling | expand |
On Mon, Sep 17, 2018 at 12:31:02PM -0400, Emilio G. Cota wrote: > From: Paolo Bonzini <pbonzini@redhat.com> > > cpu->do_interrupt can now be called with BQL held (from > cpu->cpu_exec_interrupt) or without (from cpu_handle_exception). > > Only a few targets rely on global device state in cc->do_interrupt; > add checks to those targets to acquire the BQL if not already held. > > Cc: Aleksandar Markovic <amarkovic@wavecomp.com> > Cc: Alexander Graf <agraf@suse.de> > Cc: Anthony Green <green@moxielogic.com> > Cc: Artyom Tarasenko <atar4qemu@gmail.com> > Cc: Aurelien Jarno <aurelien@aurel32.net> > Cc: Christian Borntraeger <borntraeger@de.ibm.com> > Cc: Chris Wulff <crwulff@gmail.com> > Cc: Cornelia Huck <cohuck@redhat.com> > Cc: David Gibson <david@gibson.dropbear.id.au> > Cc: David Hildenbrand <david@redhat.com> > Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> > Cc: Eduardo Habkost <ehabkost@redhat.com> > Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> > Cc: James Hogan <jhogan@kernel.org> > Cc: kvm@vger.kernel.org > Cc: Laurent Vivier <laurent@vivier.eu> > Cc: Marcelo Tosatti <mtosatti@redhat.com> > Cc: Marek Vasut <marex@denx.de> > Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> > Cc: Michael Walle <michael@walle.cc> > Cc: Peter Crosthwaite <crosthwaite.peter@gmail.com> > Cc: Peter Maydell <peter.maydell@linaro.org> > Cc: qemu-arm@nongnu.org > Cc: qemu-ppc@nongnu.org > Cc: qemu-s390x@nongnu.org > Cc: Richard Henderson <rth@twiddle.net> > Cc: Stafford Horne <shorne@gmail.com> > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> > Signed-off-by: Emilio G. Cota <cota@braap.org> ppc parts Acked-by: David Gibson <david@gibson.dropbear.id.au> > --- > accel/tcg/cpu-exec.c | 2 -- > target/arm/helper.c | 28 ++++++++++++++++++++++++++-- > target/ppc/excp_helper.c | 8 +++++++- > target/s390x/excp_helper.c | 14 +++++++++++++- > target/sh4/helper.c | 14 +++++++++++++- > target/xtensa/helper.c | 16 ++++++++++++++-- > 6 files changed, 73 insertions(+), 9 deletions(-) > > diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c > index 2383763f9b..b649e3d772 100644 > --- a/accel/tcg/cpu-exec.c > +++ b/accel/tcg/cpu-exec.c > @@ -497,9 +497,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) > #else > if (replay_exception()) { > CPUClass *cc = CPU_GET_CLASS(cpu); > - qemu_mutex_lock_iothread(); > cc->do_interrupt(cpu); > - qemu_mutex_unlock_iothread(); > cpu->exception_index = -1; > } else if (!replay_has_interrupt()) { > /* give a chance to iothread in replay mode */ > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 22dbc42305..548278da14 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -7644,7 +7644,8 @@ gen_invep: > return false; > } > > -void arm_v7m_cpu_do_interrupt(CPUState *cs) > +/* call with the BQL held */ > +static void arm_v7m_cpu_do_interrupt_locked(CPUState *cs) > { > ARMCPU *cpu = ARM_CPU(cs); > CPUARMState *env = &cpu->env; > @@ -7828,6 +7829,17 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) > v7m_exception_taken(cpu, lr, false, ignore_stackfaults); > } > > +void arm_v7m_cpu_do_interrupt(CPUState *cs) > +{ > + if (qemu_mutex_iothread_locked()) { > + arm_v7m_cpu_do_interrupt_locked(cs); > + } else { > + qemu_mutex_lock_iothread(); > + arm_v7m_cpu_do_interrupt_locked(cs); > + qemu_mutex_unlock_iothread(); > + } > +} > + > /* Function used to synchronize QEMU's AArch64 register set with AArch32 > * register set. This is necessary when switching between AArch32 and AArch64 > * execution state. > @@ -8482,8 +8494,9 @@ static inline bool check_for_semihosting(CPUState *cs) > * Do any appropriate logging, handle PSCI calls, and then hand off > * to the AArch64-entry or AArch32-entry function depending on the > * target exception level's register width. > + * Call with the BQL held. > */ > -void arm_cpu_do_interrupt(CPUState *cs) > +static void arm_cpu_do_interrupt_locked(CPUState *cs) > { > ARMCPU *cpu = ARM_CPU(cs); > CPUARMState *env = &cpu->env; > @@ -8534,6 +8547,17 @@ void arm_cpu_do_interrupt(CPUState *cs) > } > } > > +void arm_cpu_do_interrupt(CPUState *cs) > +{ > + if (qemu_mutex_iothread_locked()) { > + arm_cpu_do_interrupt_locked(cs); > + } else { > + qemu_mutex_lock_iothread(); > + arm_cpu_do_interrupt_locked(cs); > + qemu_mutex_unlock_iothread(); > + } > +} > + > /* Return the exception level which controls this address translation regime */ > static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) > { > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > index 70ac10e23b..8b2cc48cad 100644 > --- a/target/ppc/excp_helper.c > +++ b/target/ppc/excp_helper.c > @@ -742,7 +742,13 @@ void ppc_cpu_do_interrupt(CPUState *cs) > PowerPCCPU *cpu = POWERPC_CPU(cs); > CPUPPCState *env = &cpu->env; > > - powerpc_excp(cpu, env->excp_model, cs->exception_index); > + if (qemu_mutex_iothread_locked()) { > + powerpc_excp(cpu, env->excp_model, cs->exception_index); > + } else { > + qemu_mutex_lock_iothread(); > + powerpc_excp(cpu, env->excp_model, cs->exception_index); > + qemu_mutex_unlock_iothread(); > + } > } > > static void ppc_hw_interrupt(CPUPPCState *env) > diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c > index f2b92d7cbc..931c0103c8 100644 > --- a/target/s390x/excp_helper.c > +++ b/target/s390x/excp_helper.c > @@ -378,7 +378,8 @@ static void do_mchk_interrupt(CPUS390XState *env) > load_psw(env, mask, addr); > } > > -void s390_cpu_do_interrupt(CPUState *cs) > +/* call with the BQL held */ > +static void s390_cpu_do_interrupt_locked(CPUState *cs) > { > QEMUS390FLICState *flic = QEMU_S390_FLIC(s390_get_flic()); > S390CPU *cpu = S390_CPU(cs); > @@ -457,6 +458,17 @@ try_deliver: > } > } > > +void s390_cpu_do_interrupt(CPUState *cs) > +{ > + if (qemu_mutex_iothread_locked()) { > + s390_cpu_do_interrupt_locked(cs); > + } else { > + qemu_mutex_lock_iothread(); > + s390_cpu_do_interrupt_locked(cs); > + qemu_mutex_unlock_iothread(); > + } > +} > + > bool s390_cpu_exec_interrupt(CPUState *cs, int interrupt_request) > { > if (interrupt_request & CPU_INTERRUPT_HARD) { > diff --git a/target/sh4/helper.c b/target/sh4/helper.c > index c699b8c0a1..6c508cd006 100644 > --- a/target/sh4/helper.c > +++ b/target/sh4/helper.c > @@ -79,7 +79,8 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) > #define MMU_DADDR_ERROR_READ (-12) > #define MMU_DADDR_ERROR_WRITE (-13) > > -void superh_cpu_do_interrupt(CPUState *cs) > +/* call with the BQL held */ > +static void superh_cpu_do_interrupt_locked(CPUState *cs) > { > SuperHCPU *cpu = SUPERH_CPU(cs); > CPUSH4State *env = &cpu->env; > @@ -211,6 +212,17 @@ void superh_cpu_do_interrupt(CPUState *cs) > } > } > > +void superh_cpu_do_interrupt(CPUState *cs) > +{ > + if (qemu_mutex_iothread_locked()) { > + superh_cpu_do_interrupt_locked(cs); > + } else { > + qemu_mutex_lock_iothread(); > + superh_cpu_do_interrupt_locked(cs); > + qemu_mutex_unlock_iothread(); > + } > +} > + > static void update_itlb_use(CPUSH4State * env, int itlbnb) > { > uint8_t or_mask = 0, and_mask = (uint8_t) - 1; > diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c > index c9a6132700..ecafecdd3f 100644 > --- a/target/xtensa/helper.c > +++ b/target/xtensa/helper.c > @@ -26,6 +26,7 @@ > */ > > #include "qemu/osdep.h" > +#include "qemu/main-loop.h" > #include "qemu/units.h" > #include "cpu.h" > #include "exec/exec-all.h" > @@ -251,8 +252,8 @@ static void handle_interrupt(CPUXtensaState *env) > } > } > > -/* Called from cpu_handle_interrupt with BQL held */ > -void xtensa_cpu_do_interrupt(CPUState *cs) > +/* Call with the BQL held */ > +static void xtensa_cpu_do_interrupt_locked(CPUState *cs) > { > XtensaCPU *cpu = XTENSA_CPU(cs); > CPUXtensaState *env = &cpu->env; > @@ -305,6 +306,17 @@ void xtensa_cpu_do_interrupt(CPUState *cs) > } > check_interrupts(env); > } > + > +void xtensa_cpu_do_interrupt(CPUState *cs) > +{ > + if (qemu_mutex_iothread_locked()) { > + xtensa_cpu_do_interrupt_locked(cs); > + } else { > + qemu_mutex_lock_iothread(); > + xtensa_cpu_do_interrupt_locked(cs); > + qemu_mutex_unlock_iothread(); > + } > +} > #else > void xtensa_cpu_do_interrupt(CPUState *cs) > {
Am 17.09.18 um 18:31 schrieb Emilio G. Cota: > From: Paolo Bonzini <pbonzini@redhat.com> > > cpu->do_interrupt can now be called with BQL held (from > cpu->cpu_exec_interrupt) or without (from cpu_handle_exception). > > Only a few targets rely on global device state in cc->do_interrupt; > add checks to those targets to acquire the BQL if not already held. > > Cc: Aleksandar Markovic <amarkovic@wavecomp.com> > Cc: Alexander Graf <agraf@suse.de> > Cc: Anthony Green <green@moxielogic.com> > Cc: Artyom Tarasenko <atar4qemu@gmail.com> > Cc: Aurelien Jarno <aurelien@aurel32.net> > Cc: Christian Borntraeger <borntraeger@de.ibm.com> > Cc: Chris Wulff <crwulff@gmail.com> > Cc: Cornelia Huck <cohuck@redhat.com> > Cc: David Gibson <david@gibson.dropbear.id.au> > Cc: David Hildenbrand <david@redhat.com> > Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> > Cc: Eduardo Habkost <ehabkost@redhat.com> > Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> > Cc: James Hogan <jhogan@kernel.org> > Cc: kvm@vger.kernel.org > Cc: Laurent Vivier <laurent@vivier.eu> > Cc: Marcelo Tosatti <mtosatti@redhat.com> > Cc: Marek Vasut <marex@denx.de> > Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> > Cc: Michael Walle <michael@walle.cc> > Cc: Peter Crosthwaite <crosthwaite.peter@gmail.com> > Cc: Peter Maydell <peter.maydell@linaro.org> > Cc: qemu-arm@nongnu.org > Cc: qemu-ppc@nongnu.org > Cc: qemu-s390x@nongnu.org > Cc: Richard Henderson <rth@twiddle.net> > Cc: Stafford Horne <shorne@gmail.com> > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> > Signed-off-by: Emilio G. Cota <cota@braap.org> > --- > accel/tcg/cpu-exec.c | 2 -- > target/arm/helper.c | 28 ++++++++++++++++++++++++++-- > target/ppc/excp_helper.c | 8 +++++++- > target/s390x/excp_helper.c | 14 +++++++++++++- > target/sh4/helper.c | 14 +++++++++++++- > target/xtensa/helper.c | 16 ++++++++++++++-- > 6 files changed, 73 insertions(+), 9 deletions(-) > > diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c > index 2383763f9b..b649e3d772 100644 > --- a/accel/tcg/cpu-exec.c > +++ b/accel/tcg/cpu-exec.c > @@ -497,9 +497,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) > #else > if (replay_exception()) { > CPUClass *cc = CPU_GET_CLASS(cpu); > - qemu_mutex_lock_iothread(); > cc->do_interrupt(cpu); > - qemu_mutex_unlock_iothread(); > cpu->exception_index = -1; > } else if (!replay_has_interrupt()) { > /* give a chance to iothread in replay mode */ > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 22dbc42305..548278da14 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -7644,7 +7644,8 @@ gen_invep: > return false; > } > > -void arm_v7m_cpu_do_interrupt(CPUState *cs) > +/* call with the BQL held */ > +static void arm_v7m_cpu_do_interrupt_locked(CPUState *cs) > { > ARMCPU *cpu = ARM_CPU(cs); > CPUARMState *env = &cpu->env; > @@ -7828,6 +7829,17 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) > v7m_exception_taken(cpu, lr, false, ignore_stackfaults); > } > > +void arm_v7m_cpu_do_interrupt(CPUState *cs) > +{ > + if (qemu_mutex_iothread_locked()) { > + arm_v7m_cpu_do_interrupt_locked(cs); > + } else { > + qemu_mutex_lock_iothread(); > + arm_v7m_cpu_do_interrupt_locked(cs); > + qemu_mutex_unlock_iothread(); > + } > +} > + > /* Function used to synchronize QEMU's AArch64 register set with AArch32 > * register set. This is necessary when switching between AArch32 and AArch64 > * execution state. > @@ -8482,8 +8494,9 @@ static inline bool check_for_semihosting(CPUState *cs) > * Do any appropriate logging, handle PSCI calls, and then hand off > * to the AArch64-entry or AArch32-entry function depending on the > * target exception level's register width. > + * Call with the BQL held. > */ > -void arm_cpu_do_interrupt(CPUState *cs) > +static void arm_cpu_do_interrupt_locked(CPUState *cs) > { > ARMCPU *cpu = ARM_CPU(cs); > CPUARMState *env = &cpu->env; > @@ -8534,6 +8547,17 @@ void arm_cpu_do_interrupt(CPUState *cs) > } > } > > +void arm_cpu_do_interrupt(CPUState *cs) > +{ > + if (qemu_mutex_iothread_locked()) { > + arm_cpu_do_interrupt_locked(cs); > + } else { > + qemu_mutex_lock_iothread(); > + arm_cpu_do_interrupt_locked(cs); > + qemu_mutex_unlock_iothread(); > + } > +} > + > /* Return the exception level which controls this address translation regime */ > static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) > { > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > index 70ac10e23b..8b2cc48cad 100644 > --- a/target/ppc/excp_helper.c > +++ b/target/ppc/excp_helper.c > @@ -742,7 +742,13 @@ void ppc_cpu_do_interrupt(CPUState *cs) > PowerPCCPU *cpu = POWERPC_CPU(cs); > CPUPPCState *env = &cpu->env; > > - powerpc_excp(cpu, env->excp_model, cs->exception_index); > + if (qemu_mutex_iothread_locked()) { > + powerpc_excp(cpu, env->excp_model, cs->exception_index); > + } else { > + qemu_mutex_lock_iothread(); > + powerpc_excp(cpu, env->excp_model, cs->exception_index); > + qemu_mutex_unlock_iothread(); > + } > } > > static void ppc_hw_interrupt(CPUPPCState *env) > diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c > index f2b92d7cbc..931c0103c8 100644 > --- a/target/s390x/excp_helper.c > +++ b/target/s390x/excp_helper.c > @@ -378,7 +378,8 @@ static void do_mchk_interrupt(CPUS390XState *env) > load_psw(env, mask, addr); > } > > -void s390_cpu_do_interrupt(CPUState *cs) > +/* call with the BQL held */ > +static void s390_cpu_do_interrupt_locked(CPUState *cs) > { > QEMUS390FLICState *flic = QEMU_S390_FLIC(s390_get_flic()); > S390CPU *cpu = S390_CPU(cs); > @@ -457,6 +458,17 @@ try_deliver: > } > } > > +void s390_cpu_do_interrupt(CPUState *cs) > +{ > + if (qemu_mutex_iothread_locked()) { > + s390_cpu_do_interrupt_locked(cs); > + } else { > + qemu_mutex_lock_iothread(); > + s390_cpu_do_interrupt_locked(cs); > + qemu_mutex_unlock_iothread(); > + } > +} > + Yes, due to floating interrupts we need the iothread lock. This change looks sane to me from an s390x perspective: Reviewed-by: David Hildenbrand <david@redhat.com>
On Mon, 17 Sep 2018 12:31:02 -0400 "Emilio G. Cota" <cota@braap.org> wrote: > From: Paolo Bonzini <pbonzini@redhat.com> > > cpu->do_interrupt can now be called with BQL held (from > cpu->cpu_exec_interrupt) or without (from cpu_handle_exception). > > Only a few targets rely on global device state in cc->do_interrupt; > add checks to those targets to acquire the BQL if not already held. > > Cc: Aleksandar Markovic <amarkovic@wavecomp.com> > Cc: Alexander Graf <agraf@suse.de> > Cc: Anthony Green <green@moxielogic.com> > Cc: Artyom Tarasenko <atar4qemu@gmail.com> > Cc: Aurelien Jarno <aurelien@aurel32.net> > Cc: Christian Borntraeger <borntraeger@de.ibm.com> > Cc: Chris Wulff <crwulff@gmail.com> > Cc: Cornelia Huck <cohuck@redhat.com> > Cc: David Gibson <david@gibson.dropbear.id.au> > Cc: David Hildenbrand <david@redhat.com> > Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> > Cc: Eduardo Habkost <ehabkost@redhat.com> > Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> > Cc: James Hogan <jhogan@kernel.org> > Cc: kvm@vger.kernel.org > Cc: Laurent Vivier <laurent@vivier.eu> > Cc: Marcelo Tosatti <mtosatti@redhat.com> > Cc: Marek Vasut <marex@denx.de> > Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> > Cc: Michael Walle <michael@walle.cc> > Cc: Peter Crosthwaite <crosthwaite.peter@gmail.com> > Cc: Peter Maydell <peter.maydell@linaro.org> > Cc: qemu-arm@nongnu.org > Cc: qemu-ppc@nongnu.org > Cc: qemu-s390x@nongnu.org > Cc: Richard Henderson <rth@twiddle.net> > Cc: Stafford Horne <shorne@gmail.com> > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> > Signed-off-by: Emilio G. Cota <cota@braap.org> > --- > accel/tcg/cpu-exec.c | 2 -- > target/arm/helper.c | 28 ++++++++++++++++++++++++++-- > target/ppc/excp_helper.c | 8 +++++++- > target/s390x/excp_helper.c | 14 +++++++++++++- > target/sh4/helper.c | 14 +++++++++++++- > target/xtensa/helper.c | 16 ++++++++++++++-- > 6 files changed, 73 insertions(+), 9 deletions(-) s390x parts: Reviewed-by: Cornelia Huck <cohuck@redhat.com>
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2383763f9b..b649e3d772 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -497,9 +497,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) #else if (replay_exception()) { CPUClass *cc = CPU_GET_CLASS(cpu); - qemu_mutex_lock_iothread(); cc->do_interrupt(cpu); - qemu_mutex_unlock_iothread(); cpu->exception_index = -1; } else if (!replay_has_interrupt()) { /* give a chance to iothread in replay mode */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 22dbc42305..548278da14 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7644,7 +7644,8 @@ gen_invep: return false; } -void arm_v7m_cpu_do_interrupt(CPUState *cs) +/* call with the BQL held */ +static void arm_v7m_cpu_do_interrupt_locked(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; @@ -7828,6 +7829,17 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) v7m_exception_taken(cpu, lr, false, ignore_stackfaults); } +void arm_v7m_cpu_do_interrupt(CPUState *cs) +{ + if (qemu_mutex_iothread_locked()) { + arm_v7m_cpu_do_interrupt_locked(cs); + } else { + qemu_mutex_lock_iothread(); + arm_v7m_cpu_do_interrupt_locked(cs); + qemu_mutex_unlock_iothread(); + } +} + /* Function used to synchronize QEMU's AArch64 register set with AArch32 * register set. This is necessary when switching between AArch32 and AArch64 * execution state. @@ -8482,8 +8494,9 @@ static inline bool check_for_semihosting(CPUState *cs) * Do any appropriate logging, handle PSCI calls, and then hand off * to the AArch64-entry or AArch32-entry function depending on the * target exception level's register width. + * Call with the BQL held. */ -void arm_cpu_do_interrupt(CPUState *cs) +static void arm_cpu_do_interrupt_locked(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; @@ -8534,6 +8547,17 @@ void arm_cpu_do_interrupt(CPUState *cs) } } +void arm_cpu_do_interrupt(CPUState *cs) +{ + if (qemu_mutex_iothread_locked()) { + arm_cpu_do_interrupt_locked(cs); + } else { + qemu_mutex_lock_iothread(); + arm_cpu_do_interrupt_locked(cs); + qemu_mutex_unlock_iothread(); + } +} + /* Return the exception level which controls this address translation regime */ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) { diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 70ac10e23b..8b2cc48cad 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -742,7 +742,13 @@ void ppc_cpu_do_interrupt(CPUState *cs) PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; - powerpc_excp(cpu, env->excp_model, cs->exception_index); + if (qemu_mutex_iothread_locked()) { + powerpc_excp(cpu, env->excp_model, cs->exception_index); + } else { + qemu_mutex_lock_iothread(); + powerpc_excp(cpu, env->excp_model, cs->exception_index); + qemu_mutex_unlock_iothread(); + } } static void ppc_hw_interrupt(CPUPPCState *env) diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index f2b92d7cbc..931c0103c8 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -378,7 +378,8 @@ static void do_mchk_interrupt(CPUS390XState *env) load_psw(env, mask, addr); } -void s390_cpu_do_interrupt(CPUState *cs) +/* call with the BQL held */ +static void s390_cpu_do_interrupt_locked(CPUState *cs) { QEMUS390FLICState *flic = QEMU_S390_FLIC(s390_get_flic()); S390CPU *cpu = S390_CPU(cs); @@ -457,6 +458,17 @@ try_deliver: } } +void s390_cpu_do_interrupt(CPUState *cs) +{ + if (qemu_mutex_iothread_locked()) { + s390_cpu_do_interrupt_locked(cs); + } else { + qemu_mutex_lock_iothread(); + s390_cpu_do_interrupt_locked(cs); + qemu_mutex_unlock_iothread(); + } +} + bool s390_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { diff --git a/target/sh4/helper.c b/target/sh4/helper.c index c699b8c0a1..6c508cd006 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -79,7 +79,8 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) #define MMU_DADDR_ERROR_READ (-12) #define MMU_DADDR_ERROR_WRITE (-13) -void superh_cpu_do_interrupt(CPUState *cs) +/* call with the BQL held */ +static void superh_cpu_do_interrupt_locked(CPUState *cs) { SuperHCPU *cpu = SUPERH_CPU(cs); CPUSH4State *env = &cpu->env; @@ -211,6 +212,17 @@ void superh_cpu_do_interrupt(CPUState *cs) } } +void superh_cpu_do_interrupt(CPUState *cs) +{ + if (qemu_mutex_iothread_locked()) { + superh_cpu_do_interrupt_locked(cs); + } else { + qemu_mutex_lock_iothread(); + superh_cpu_do_interrupt_locked(cs); + qemu_mutex_unlock_iothread(); + } +} + static void update_itlb_use(CPUSH4State * env, int itlbnb) { uint8_t or_mask = 0, and_mask = (uint8_t) - 1; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index c9a6132700..ecafecdd3f 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -26,6 +26,7 @@ */ #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "qemu/units.h" #include "cpu.h" #include "exec/exec-all.h" @@ -251,8 +252,8 @@ static void handle_interrupt(CPUXtensaState *env) } } -/* Called from cpu_handle_interrupt with BQL held */ -void xtensa_cpu_do_interrupt(CPUState *cs) +/* Call with the BQL held */ +static void xtensa_cpu_do_interrupt_locked(CPUState *cs) { XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; @@ -305,6 +306,17 @@ void xtensa_cpu_do_interrupt(CPUState *cs) } check_interrupts(env); } + +void xtensa_cpu_do_interrupt(CPUState *cs) +{ + if (qemu_mutex_iothread_locked()) { + xtensa_cpu_do_interrupt_locked(cs); + } else { + qemu_mutex_lock_iothread(); + xtensa_cpu_do_interrupt_locked(cs); + qemu_mutex_unlock_iothread(); + } +} #else void xtensa_cpu_do_interrupt(CPUState *cs) {