Message ID | 1537530911-443-3-git-send-email-fabrizio.castro@bp.renesas.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add SDHI2 support to iwg23s | expand |
On Fri, Sep 21, 2018 at 12:55:09PM +0100, Fabrizio Castro wrote: > Add SH_PFC_PIN_CFG_IO_VOLTAGE definition for the SDHI2 pins > capable of switching voltage. Please note that with the > RZ/G1C only 1 bit of the POC Control Register is used to > control each interface. > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > Reviewed-by: Biju Das <biju.das@bp.renesas.com> In general: Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > + if (_bank == 4 && _pin >= 14 && _pin <= 19) > + return 1; > + > + return -EINVAL; I'd like a tad better to bail out on the error case and have the main path returning on the good case, but no strong opinion...
On Sat, Sep 22, 2018 at 8:44 PM Wolfram Sang <wsa@the-dreams.de> wrote: > On Fri, Sep 21, 2018 at 12:55:09PM +0100, Fabrizio Castro wrote: > > Add SH_PFC_PIN_CFG_IO_VOLTAGE definition for the SDHI2 pins > > capable of switching voltage. Please note that with the > > RZ/G1C only 1 bit of the POC Control Register is used to > > control each interface. > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > Reviewed-by: Biju Das <biju.das@bp.renesas.com> > > In general: > > Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > > > + if (_bank == 4 && _pin >= 14 && _pin <= 19) > > + return 1; > > + > > + return -EINVAL; > > I'd like a tad better to bail out on the error case and have the main > path returning on the good case, but no strong opinion... And we have these nice RCAR_GP_PIN() macros to check pin ranges. Please have a look at the flow in e.g. r8a7795_pin_to_pocctrl(). Gr{oetje,eeting}s, Geert
Hello Geert, hello Wolfram, Thank you both for your feedback. > Subject: Re: [PATCH 2/4] pinctrl: sh-pfc: r8a77470: Add SDHI2 voltage switch > > On Sat, Sep 22, 2018 at 8:44 PM Wolfram Sang <wsa@the-dreams.de> wrote: > > On Fri, Sep 21, 2018 at 12:55:09PM +0100, Fabrizio Castro wrote: > > > Add SH_PFC_PIN_CFG_IO_VOLTAGE definition for the SDHI2 pins > > > capable of switching voltage. Please note that with the > > > RZ/G1C only 1 bit of the POC Control Register is used to > > > control each interface. > > > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > > Reviewed-by: Biju Das <biju.das@bp.renesas.com> > > > > In general: > > > > Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > > > > > + if (_bank == 4 && _pin >= 14 && _pin <= 19) > > > + return 1; > > > + > > > + return -EINVAL; > > > > I'd like a tad better to bail out on the error case and have the main > > path returning on the good case, but no strong opinion... > > And we have these nice RCAR_GP_PIN() macros to check pin ranges. > Please have a look at the flow in e.g. r8a7795_pin_to_pocctrl(). I'll send a v2 to address this, thank you for pointing me to the right direction. Cheers, Fab > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index 9d3ed43..a1248e2 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -17,7 +17,19 @@ PORT_GP_1(3, 27, fn, sfx), \ PORT_GP_1(3, 28, fn, sfx), \ PORT_GP_1(3, 29, fn, sfx), \ - PORT_GP_26(4, fn, sfx), \ + PORT_GP_14(4, fn, sfx), \ + PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_1(4, 20, fn, sfx), \ + PORT_GP_1(4, 21, fn, sfx), \ + PORT_GP_1(4, 22, fn, sfx), \ + PORT_GP_1(4, 23, fn, sfx), \ + PORT_GP_1(4, 24, fn, sfx), \ + PORT_GP_1(4, 25, fn, sfx), \ PORT_GP_32(5, fn, sfx) enum { @@ -2321,9 +2333,27 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, + u32 *pocctrl) +{ + unsigned int _bank = pin >> 5; + unsigned int _pin = pin & 0x1f; + *pocctrl = 0xe60600b0; + + if (_bank == 4 && _pin >= 14 && _pin <= 19) + return 1; + + return -EINVAL; +} + +static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = { + .pin_to_pocctrl = r8a77470_pin_to_pocctrl, +}; + #ifdef CONFIG_PINCTRL_PFC_R8A77470 const struct sh_pfc_soc_info r8a77470_pinmux_info = { .name = "r8a77470_pfc", + .ops = &r8a77470_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },