| Message ID | 1537150762-7072-2-git-send-email-leilk.liu@mediatek.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add Mediatek SPI slave driver | expand |
On Wed, 2018-09-26 at 17:33 -0500, Rob Herring wrote: > On Mon, Sep 17, 2018 at 10:19:20AM +0800, Leilk Liu wrote: > > This patch adds a DT binding documentation for the MT2712 soc. > > > > Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> > > --- > > .../devicetree/bindings/spi/spi-slave-mt27xx.txt | 32 ++++++++++++++++++++ > > 1 file changed, 32 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt > > > > diff --git a/Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt b/Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt > > new file mode 100644 > > index 0000000..09cb2c4 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt > > @@ -0,0 +1,32 @@ > > +Binding for MTK SPI Slave controller > > + > > +Required properties: > > +- compatible: should be one of the following. > > + - mediatek,mt2712-spi-slave: for mt2712 platforms > > +- reg: Address and length of the register set for the device. > > +- interrupts: Should contain spi interrupt. > > +- clocks: phandles to input clocks. > > + It's clock gate, and should be <&infracfg CLK_INFRA_AO_SPI1>. > > +- clock-names: should be "spi" for the clock gate. > > + > > +Optional properties: > > +- assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>. > > +- assigned-clock-parents: parent of mux clock. > > + It's PLL, and should be on of the following. > > s/on/one/ > > With that fixed, > > Reviewed-by: Rob Herring <robh@kernel.org> Yes, it's a mistake, I'll fix it, thanks
diff --git a/Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt b/Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt new file mode 100644 index 0000000..09cb2c4 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt @@ -0,0 +1,32 @@ +Binding for MTK SPI Slave controller + +Required properties: +- compatible: should be one of the following. + - mediatek,mt2712-spi-slave: for mt2712 platforms +- reg: Address and length of the register set for the device. +- interrupts: Should contain spi interrupt. +- clocks: phandles to input clocks. + It's clock gate, and should be <&infracfg CLK_INFRA_AO_SPI1>. +- clock-names: should be "spi" for the clock gate. + +Optional properties: +- assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>. +- assigned-clock-parents: parent of mux clock. + It's PLL, and should be on of the following. + - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ. + It's the default one. + - <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ. + - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ. + - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ. + +Example: +- SoC Specific Portion: +spis1: spi@10013000 { + compatible = "mediatek,mt2712-spi-slave"; + reg = <0 0x10013000 0 0x100>; + interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_AO_SPI1>; + clock-names = "spi"; + assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; +};
This patch adds a DT binding documentation for the MT2712 soc. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> --- .../devicetree/bindings/spi/spi-slave-mt27xx.txt | 32 ++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt