Message ID | 20181003072203.12848-5-mahesh1.kumar@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Refactor and Add helper function for combophy/tc ports | expand |
On Wed, Oct 03, 2018 at 12:51:59PM +0530, Mahesh Kumar wrote: > From: Vandita Kulkarni <vandita.kulkarni@intel.com> > > Use intel_port_is_tc and intel_port_is_combophy > functions to replace the individual port checks > from port C to F and port A to B respectively. > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Cc: Madhav Chauhan <madhav.chauhan@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 15 ++++----------- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 14 ++++---------- > 2 files changed, 8 insertions(+), 21 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 16d9a20a420a..e31d71526afd 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -9296,24 +9296,17 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv, > u32 temp; > > /* TODO: TBT pll not implemented. */ > - switch (port) { > - case PORT_A: > - case PORT_B: > + if (intel_port_is_combophy(dev_priv, port)) { > temp = I915_READ(DPCLKA_CFGCR0_ICL) & > DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); > id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); > > if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1)) > return; > - break; > - case PORT_C: > - case PORT_D: > - case PORT_E: > - case PORT_F: > + } else if (intel_port_is_tc(dev_priv, port)) { > id = icl_port_to_mg_pll_id(port); > - break; > - default: > - MISSING_CASE(port); > + } else { > + WARN(1, "Invalid port %x\n", port); > return; > } > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index 510ea90f6f5b..5b2ee49aee14 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -2874,6 +2874,7 @@ static struct intel_shared_dpll * > icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, > struct intel_encoder *encoder) > { > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_digital_port *intel_dig_port = > enc_to_dig_port(&encoder->base); > struct intel_shared_dpll *pll; > @@ -2883,18 +2884,12 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, > int clock = crtc_state->port_clock; > bool ret; > > - switch (port) { > - case PORT_A: > - case PORT_B: > + if (intel_port_is_combophy(dev_priv, port)) { > min = DPLL_ID_ICL_DPLL0; > max = DPLL_ID_ICL_DPLL1; > ret = icl_calc_dpll_state(crtc_state, encoder, clock, > &pll_state); > - break; > - case PORT_C: > - case PORT_D: > - case PORT_E: > - case PORT_F: > + } else if (intel_port_is_tc(dev_priv, port)) { > if (intel_dig_port->tc_type == TC_PORT_TBT) { > min = DPLL_ID_ICL_TBTPLL; > max = min; > @@ -2906,8 +2901,7 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, > ret = icl_calc_mg_pll_state(crtc_state, encoder, clock, > &pll_state); > } > - break; > - default: > + } else { > MISSING_CASE(port); > return NULL; > } > -- > 2.16.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, Oct 03, 2018 at 12:51:59PM +0530, Mahesh Kumar wrote: > From: Vandita Kulkarni <vandita.kulkarni@intel.com> > > Use intel_port_is_tc and intel_port_is_combophy > functions to replace the individual port checks > from port C to F and port A to B respectively. > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Cc: Madhav Chauhan <madhav.chauhan@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Lucas De Marchi > --- > drivers/gpu/drm/i915/intel_display.c | 15 ++++----------- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 14 ++++---------- > 2 files changed, 8 insertions(+), 21 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 16d9a20a420a..e31d71526afd 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -9296,24 +9296,17 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv, > u32 temp; > > /* TODO: TBT pll not implemented. */ > - switch (port) { > - case PORT_A: > - case PORT_B: > + if (intel_port_is_combophy(dev_priv, port)) { > temp = I915_READ(DPCLKA_CFGCR0_ICL) & > DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); > id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); > > if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1)) > return; > - break; > - case PORT_C: > - case PORT_D: > - case PORT_E: > - case PORT_F: > + } else if (intel_port_is_tc(dev_priv, port)) { > id = icl_port_to_mg_pll_id(port); > - break; > - default: > - MISSING_CASE(port); > + } else { > + WARN(1, "Invalid port %x\n", port); > return; > } > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index 510ea90f6f5b..5b2ee49aee14 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -2874,6 +2874,7 @@ static struct intel_shared_dpll * > icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, > struct intel_encoder *encoder) > { > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_digital_port *intel_dig_port = > enc_to_dig_port(&encoder->base); > struct intel_shared_dpll *pll; > @@ -2883,18 +2884,12 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, > int clock = crtc_state->port_clock; > bool ret; > > - switch (port) { > - case PORT_A: > - case PORT_B: > + if (intel_port_is_combophy(dev_priv, port)) { > min = DPLL_ID_ICL_DPLL0; > max = DPLL_ID_ICL_DPLL1; > ret = icl_calc_dpll_state(crtc_state, encoder, clock, > &pll_state); > - break; > - case PORT_C: > - case PORT_D: > - case PORT_E: > - case PORT_F: > + } else if (intel_port_is_tc(dev_priv, port)) { > if (intel_dig_port->tc_type == TC_PORT_TBT) { > min = DPLL_ID_ICL_TBTPLL; > max = min; > @@ -2906,8 +2901,7 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, > ret = icl_calc_mg_pll_state(crtc_state, encoder, clock, > &pll_state); > } > - break; > - default: > + } else { > MISSING_CASE(port); > return NULL; > } > -- > 2.16.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 16d9a20a420a..e31d71526afd 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9296,24 +9296,17 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv, u32 temp; /* TODO: TBT pll not implemented. */ - switch (port) { - case PORT_A: - case PORT_B: + if (intel_port_is_combophy(dev_priv, port)) { temp = I915_READ(DPCLKA_CFGCR0_ICL) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1)) return; - break; - case PORT_C: - case PORT_D: - case PORT_E: - case PORT_F: + } else if (intel_port_is_tc(dev_priv, port)) { id = icl_port_to_mg_pll_id(port); - break; - default: - MISSING_CASE(port); + } else { + WARN(1, "Invalid port %x\n", port); return; } diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 510ea90f6f5b..5b2ee49aee14 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -2874,6 +2874,7 @@ static struct intel_shared_dpll * icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); struct intel_shared_dpll *pll; @@ -2883,18 +2884,12 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, int clock = crtc_state->port_clock; bool ret; - switch (port) { - case PORT_A: - case PORT_B: + if (intel_port_is_combophy(dev_priv, port)) { min = DPLL_ID_ICL_DPLL0; max = DPLL_ID_ICL_DPLL1; ret = icl_calc_dpll_state(crtc_state, encoder, clock, &pll_state); - break; - case PORT_C: - case PORT_D: - case PORT_E: - case PORT_F: + } else if (intel_port_is_tc(dev_priv, port)) { if (intel_dig_port->tc_type == TC_PORT_TBT) { min = DPLL_ID_ICL_TBTPLL; max = min; @@ -2906,8 +2901,7 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, ret = icl_calc_mg_pll_state(crtc_state, encoder, clock, &pll_state); } - break; - default: + } else { MISSING_CASE(port); return NULL; }