| Message ID | 1538579266-8389-10-git-send-email-edgar.iglesias@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm: Add first models of Xilinx Versal SoC | expand |
On 3 October 2018 at 16:07, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > When QEMU provides the equivalent of the EL3 firmware, we > need to enable HVCs in scr_el3 when turning on CPUs that > target EL2. > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > --- > target/arm/arm-powerctl.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c > index ce55eeb..54f2974 100644 > --- a/target/arm/arm-powerctl.c > +++ b/target/arm/arm-powerctl.c > @@ -63,6 +63,7 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, > struct CpuOnInfo *info = (struct CpuOnInfo *) data.host_ptr; > > /* Initialize the cpu we are turning on */ > + qemu_log("CPU%d reset\n", target_cpu_state->cpu_index); qemu_log logging should always be masked to a particular log kind (either via qemu_log_mask() or by explicit check on the log level). If this was accidentally left-in debug, you could just drop it :-) > cpu_reset(target_cpu_state); > target_cpu_state->halted = 0; > > @@ -103,6 +104,16 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, > } else { > /* Processor is not in secure mode */ > target_cpu->env.cp15.scr_el3 |= SCR_NS; > + > + /* > + * If QEMU is providing the equivalent of EL3 firmware, then we need > + * to make sure a CPU targeting EL2 comes out of reset with a > + * functional HVC insn. > + */ > + if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3) > + && info->target_el == 2) { > + target_cpu->env.cp15.scr_el3 |= SCR_HCE; > + } > } Otherwise Reviewed-by: Peter Maydell <peter.maydell@linaro.org> This is definitely required for PSCI and I think it makes sense in other cases that end up in this powerctl code with EL3 set. thanks -- PMM
On Mon, Oct 08, 2018 at 01:41:36PM +0100, Peter Maydell wrote: > On 3 October 2018 at 16:07, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote: > > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > > > When QEMU provides the equivalent of the EL3 firmware, we > > need to enable HVCs in scr_el3 when turning on CPUs that > > target EL2. > > > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > > --- > > target/arm/arm-powerctl.c | 11 +++++++++++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c > > index ce55eeb..54f2974 100644 > > --- a/target/arm/arm-powerctl.c > > +++ b/target/arm/arm-powerctl.c > > @@ -63,6 +63,7 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, > > struct CpuOnInfo *info = (struct CpuOnInfo *) data.host_ptr; > > > > /* Initialize the cpu we are turning on */ > > + qemu_log("CPU%d reset\n", target_cpu_state->cpu_index); > > qemu_log logging should always be masked to a particular > log kind (either via qemu_log_mask() or by explicit check on > the log level). If this was accidentally left-in debug, you could > just drop it :-) Hah, yes this is an accidental leftover... > > > cpu_reset(target_cpu_state); > > target_cpu_state->halted = 0; > > > > @@ -103,6 +104,16 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, > > } else { > > /* Processor is not in secure mode */ > > target_cpu->env.cp15.scr_el3 |= SCR_NS; > > + > > + /* > > + * If QEMU is providing the equivalent of EL3 firmware, then we need > > + * to make sure a CPU targeting EL2 comes out of reset with a > > + * functional HVC insn. > > + */ > > + if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3) > > + && info->target_el == 2) { > > + target_cpu->env.cp15.scr_el3 |= SCR_HCE; > > + } > > } > > Otherwise > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > This is definitely required for PSCI and I think it makes sense > in other cases that end up in this powerctl code with EL3 set. Thanks, Edgar
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index ce55eeb..54f2974 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -63,6 +63,7 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, struct CpuOnInfo *info = (struct CpuOnInfo *) data.host_ptr; /* Initialize the cpu we are turning on */ + qemu_log("CPU%d reset\n", target_cpu_state->cpu_index); cpu_reset(target_cpu_state); target_cpu_state->halted = 0; @@ -103,6 +104,16 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, } else { /* Processor is not in secure mode */ target_cpu->env.cp15.scr_el3 |= SCR_NS; + + /* + * If QEMU is providing the equivalent of EL3 firmware, then we need + * to make sure a CPU targeting EL2 comes out of reset with a + * functional HVC insn. + */ + if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3) + && info->target_el == 2) { + target_cpu->env.cp15.scr_el3 |= SCR_HCE; + } } /* We check if the started CPU is now at the correct level */