| Message ID | 20181005232306.31133-27-manasi.d.navare@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Display Stream Compression enabling on eDP/DP | expand |
Hi Ville, This adds a helper function to get the power well as per the transcoder as per your suggestion. Could you please review this one? Regards Manasi On Fri, Oct 05, 2018 at 04:23:04PM -0700, Manasi Navare wrote: > A separate power well 2 (PG2) is required for VDSC on eDP transcoder > whereas all other transcoders use the power wells associated with the > transcoders for VDSC. > This patch adds a helper to obtain correct power domain depending on > transcoder being used and enables/disables the power wells during > VDSC enabling/disabling. > > Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > drivers/gpu/drm/i915/intel_vdsc.c | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c > index 4963e80a87f0..d2b4601459c3 100644 > --- a/drivers/gpu/drm/i915/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/intel_vdsc.c > @@ -581,6 +581,23 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > return 0; > } > > +static enum intel_display_power_domain > +intel_dsc_get_power_domains(struct intel_crtc_state *crtc_state) > +{ > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + > + /* > + * On ICL+ PW2/ POWER_DOMAIN_VDSC_PIPE_A is required for > + * VDSC/joining for eDP transcoder. > + * For any other transcoder, VDSC/joining uses the power well associated > + * with the pipe/transcoder in use. > + */ > + if (cpu_transcoder == TRANSCODER_EDP) > + return POWER_DOMAIN_VDSC_PIPE_A; > + else > + return POWER_DOMAIN_TRANSCODER(cpu_transcoder); > +} > + > static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > struct intel_crtc_state *crtc_state) > { > @@ -1019,6 +1036,10 @@ void intel_dsc_enable(struct intel_encoder *encoder, > if (!crtc_state->dsc_params.compression_enable) > return; > > + /* Enable Power wells for VDSC/joining */ > + intel_display_power_get(dev_priv, > + intel_dsc_get_power_domains(crtc_state)); > + > intel_configure_pps_for_dsc_encoder(encoder, crtc_state); > > intel_dp_send_dsc_pps_sdp(encoder, crtc_state); > @@ -1073,4 +1094,8 @@ void intel_dsc_disable(struct intel_encoder *encoder, > RIGHT_BRANCH_VDSC_ENABLE); > I915_WRITE(dss_ctl2_reg, dss_ctl2_val); > > + /* Disable Power wells for VDSC/joining */ > + intel_display_power_put(dev_priv, > + intel_dsc_get_power_domains(old_crtc_state)); > + > } > -- > 2.18.0 >
On Fri, Oct 05, 2018 at 04:23:04PM -0700, Manasi Navare wrote: > A separate power well 2 (PG2) is required for VDSC on eDP transcoder > whereas all other transcoders use the power wells associated with the > transcoders for VDSC. > This patch adds a helper to obtain correct power domain depending on > transcoder being used and enables/disables the power wells during > VDSC enabling/disabling. > > Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > drivers/gpu/drm/i915/intel_vdsc.c | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c > index 4963e80a87f0..d2b4601459c3 100644 > --- a/drivers/gpu/drm/i915/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/intel_vdsc.c > @@ -581,6 +581,23 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > return 0; > } > > +static enum intel_display_power_domain > +intel_dsc_get_power_domains(struct intel_crtc_state *crtc_state) crtc_state can be const. > +{ > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + > + /* > + * On ICL+ PW2/ POWER_DOMAIN_VDSC_PIPE_A is required for Tabs fail in this comment. > + * VDSC/joining for eDP transcoder. > + * For any other transcoder, VDSC/joining uses the power well associated > + * with the pipe/transcoder in use. The one thing I'd like the comment to explain is why the power domain is called PIPE_A_something but we pick it based on the transcoder. Maybe? /* * Only the eDP/DSI VDSC (ICL) and the pipe A VDSC (*something*) * have their own power well. For the other VDSCs another * reference for the transcoder (ICL) or pipe (*something*) will * suffice. * * To avoid wasting power domain bits we reuse the PIPE_A_VDSC * power domain for both the eDP/DSI VDSC (ICL) and the * pipe A VDSC (*something*). */ Not sure if we can fill the *something* yet :) Or maybe with the aliasing TRANSCODER_EDP_VDSC idea we wouldn't really need to explain so much So maybe just something simpler like /* * Only eDP/DSI VDSC has its own power well. For the other * VDSCs another reference on the transcoder power domain * will suffice. */ and then we'd add the same comment with s/transcoder/pipe/ for the next platform. Anyways, just thinking out loud. If you want you can go with what you have with the const/tabs fixed. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > + */ > + if (cpu_transcoder == TRANSCODER_EDP) > + return POWER_DOMAIN_VDSC_PIPE_A; > + else > + return POWER_DOMAIN_TRANSCODER(cpu_transcoder); > +} > + > static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > struct intel_crtc_state *crtc_state) > { > @@ -1019,6 +1036,10 @@ void intel_dsc_enable(struct intel_encoder *encoder, > if (!crtc_state->dsc_params.compression_enable) > return; > > + /* Enable Power wells for VDSC/joining */ > + intel_display_power_get(dev_priv, > + intel_dsc_get_power_domains(crtc_state)); > + > intel_configure_pps_for_dsc_encoder(encoder, crtc_state); > > intel_dp_send_dsc_pps_sdp(encoder, crtc_state); > @@ -1073,4 +1094,8 @@ void intel_dsc_disable(struct intel_encoder *encoder, > RIGHT_BRANCH_VDSC_ENABLE); > I915_WRITE(dss_ctl2_reg, dss_ctl2_val); > > + /* Disable Power wells for VDSC/joining */ > + intel_display_power_put(dev_priv, > + intel_dsc_get_power_domains(old_crtc_state)); > + > } > -- > 2.18.0
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index 4963e80a87f0..d2b4601459c3 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -581,6 +581,23 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, return 0; } +static enum intel_display_power_domain +intel_dsc_get_power_domains(struct intel_crtc_state *crtc_state) +{ + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + /* + * On ICL+ PW2/ POWER_DOMAIN_VDSC_PIPE_A is required for + * VDSC/joining for eDP transcoder. + * For any other transcoder, VDSC/joining uses the power well associated + * with the pipe/transcoder in use. + */ + if (cpu_transcoder == TRANSCODER_EDP) + return POWER_DOMAIN_VDSC_PIPE_A; + else + return POWER_DOMAIN_TRANSCODER(cpu_transcoder); +} + static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { @@ -1019,6 +1036,10 @@ void intel_dsc_enable(struct intel_encoder *encoder, if (!crtc_state->dsc_params.compression_enable) return; + /* Enable Power wells for VDSC/joining */ + intel_display_power_get(dev_priv, + intel_dsc_get_power_domains(crtc_state)); + intel_configure_pps_for_dsc_encoder(encoder, crtc_state); intel_dp_send_dsc_pps_sdp(encoder, crtc_state); @@ -1073,4 +1094,8 @@ void intel_dsc_disable(struct intel_encoder *encoder, RIGHT_BRANCH_VDSC_ENABLE); I915_WRITE(dss_ctl2_reg, dss_ctl2_val); + /* Disable Power wells for VDSC/joining */ + intel_display_power_put(dev_priv, + intel_dsc_get_power_domains(old_crtc_state)); + }
A separate power well 2 (PG2) is required for VDSC on eDP transcoder whereas all other transcoders use the power wells associated with the transcoders for VDSC. This patch adds a helper to obtain correct power domain depending on transcoder being used and enables/disables the power wells during VDSC enabling/disabling. Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/intel_vdsc.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)