| Message ID | 20181005185643.31660-2-dhinakaran.pandiyan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm/i915: Fix VIDEO_DIP_CTL bit shifts | expand |
On Fri, Oct 05, 2018 at 11:56:43AM -0700, Dhinakaran Pandiyan wrote: > The bits weren't defined in descending order. > v2: Move definitions in a separate patch (Manasi) > > Cc: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Manasi > --- > drivers/gpu/drm/i915/i915_reg.h | 19 +++++++++---------- > 1 file changed, 9 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 61148b9a4a8e..a98b95922818 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4584,6 +4584,15 @@ enum { > #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) > #define VIDEO_DIP_FREQ_MASK (3 << 16) > /* HSW and later: */ > +#define DRM_DIP_ENABLE (1 << 28) > +#define PSR_VSC_BIT_7_SET (1 << 27) > +#define VSC_SELECT_MASK (0x3 << 25) > +#define VSC_SELECT_SHIFT 25 > +#define VSC_DIP_HW_HEA_DATA (0 << 25) > +#define VSC_DIP_HW_HEA_SW_DATA (1 << 25) > +#define VSC_DIP_HW_DATA_SW_HEA (2 << 25) > +#define VSC_DIP_SW_HEA_DATA (3 << 25) > +#define VDIP_ENABLE_PPS (1 << 24) > #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) > #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) > #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) > @@ -4591,16 +4600,6 @@ enum { > #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) > #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) > > -#define DRM_DIP_ENABLE (1 << 28) > -#define PSR_VSC_BIT_7_SET (1 << 27) > -#define VSC_SELECT_MASK (0x3 << 25) > -#define VSC_SELECT_SHIFT 25 > -#define VSC_DIP_HW_HEA_DATA (0 << 25) > -#define VSC_DIP_HW_HEA_SW_DATA (1 << 25) > -#define VSC_DIP_HW_DATA_SW_HEA (2 << 25) > -#define VSC_DIP_SW_HEA_DATA (3 << 25) > -#define VDIP_ENABLE_PPS (1 << 24) > - > /* Panel power sequencing */ > #define PPS_BASE 0x61200 > #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) > -- > 2.17.1 >
On Fri, 2018-10-05 at 12:03 -0700, Manasi Navare wrote: > On Fri, Oct 05, 2018 at 11:56:43AM -0700, Dhinakaran Pandiyan wrote: > > The bits weren't defined in descending order. > > v2: Move definitions in a separate patch (Manasi) > > > > Cc: Manasi Navare <manasi.d.navare@intel.com> > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Thanks for the reviews, pushed. -DK > > Manasi > > > --- > > drivers/gpu/drm/i915/i915_reg.h | 19 +++++++++---------- > > 1 file changed, 9 insertions(+), 10 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index 61148b9a4a8e..a98b95922818 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -4584,6 +4584,15 @@ enum { > > #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) > > #define VIDEO_DIP_FREQ_MASK (3 << 16) > > /* HSW and later: */ > > +#define DRM_DIP_ENABLE (1 << 28) > > +#define PSR_VSC_BIT_7_SET (1 << 27) > > +#define VSC_SELECT_MASK (0x3 << 25) > > +#define VSC_SELECT_SHIFT 25 > > +#define VSC_DIP_HW_HEA_DATA (0 << 25) > > +#define VSC_DIP_HW_HEA_SW_DATA (1 << 25) > > +#define VSC_DIP_HW_DATA_SW_HEA (2 << 25) > > +#define VSC_DIP_SW_HEA_DATA (3 << 25) > > +#define VDIP_ENABLE_PPS (1 << 24) > > #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) > > #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) > > #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) > > @@ -4591,16 +4600,6 @@ enum { > > #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) > > #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) > > > > -#define DRM_DIP_ENABLE (1 << 28) > > -#define PSR_VSC_BIT_7_SET (1 << 27) > > -#define VSC_SELECT_MASK (0x3 << 25) > > -#define VSC_SELECT_SHIFT 25 > > -#define VSC_DIP_HW_HEA_DATA (0 << 25) > > -#define VSC_DIP_HW_HEA_SW_DATA (1 << 25) > > -#define VSC_DIP_HW_DATA_SW_HEA (2 << 25) > > -#define VSC_DIP_SW_HEA_DATA (3 << 25) > > -#define VDIP_ENABLE_PPS (1 << 24) > > - > > /* Panel power sequencing */ > > #define PPS_BASE 0x61200 > > #define VLV_PPS_BASE (VLV_DISPLAY_BASE + > > PPS_BASE) > > -- > > 2.17.1 > >
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 61148b9a4a8e..a98b95922818 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4584,6 +4584,15 @@ enum { #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) #define VIDEO_DIP_FREQ_MASK (3 << 16) /* HSW and later: */ +#define DRM_DIP_ENABLE (1 << 28) +#define PSR_VSC_BIT_7_SET (1 << 27) +#define VSC_SELECT_MASK (0x3 << 25) +#define VSC_SELECT_SHIFT 25 +#define VSC_DIP_HW_HEA_DATA (0 << 25) +#define VSC_DIP_HW_HEA_SW_DATA (1 << 25) +#define VSC_DIP_HW_DATA_SW_HEA (2 << 25) +#define VSC_DIP_SW_HEA_DATA (3 << 25) +#define VDIP_ENABLE_PPS (1 << 24) #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) @@ -4591,16 +4600,6 @@ enum { #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) -#define DRM_DIP_ENABLE (1 << 28) -#define PSR_VSC_BIT_7_SET (1 << 27) -#define VSC_SELECT_MASK (0x3 << 25) -#define VSC_SELECT_SHIFT 25 -#define VSC_DIP_HW_HEA_DATA (0 << 25) -#define VSC_DIP_HW_HEA_SW_DATA (1 << 25) -#define VSC_DIP_HW_DATA_SW_HEA (2 << 25) -#define VSC_DIP_SW_HEA_DATA (3 << 25) -#define VDIP_ENABLE_PPS (1 << 24) - /* Panel power sequencing */ #define PPS_BASE 0x61200 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
The bits weren't defined in descending order. v2: Move definitions in a separate patch (Manasi) Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-)