diff mbox series

[v3,4/4] drm/i915/icl: WaAllowUMDToModifySamplerMode

Message ID 20181030084504.21537-4-radhakrishna.sripada@intel.com (mailing list archive)
State New, archived
Headers show
Series None | expand

Commit Message

Sripada, Radhakrishna Oct. 30, 2018, 8:45 a.m. UTC 
From: Oscar Mateo <oscar.mateo@intel.com>

Required for Bindless samplers.
Userspace consumer: mesa

V2: Rebase
V3: Update commit message

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 2 ++
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 2 files changed, 5 insertions(+)

Comments

Chris Wilson Oct. 30, 2018, 9:12 a.m. UTC | #1 
Quoting Radhakrishna Sripada (2018-10-30 08:45:04)
> From: Oscar Mateo <oscar.mateo@intel.com>
> 
> Required for Bindless samplers.
> Userspace consumer: mesa
> 
> V2: Rebase
> V3: Update commit message
> 
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 2 ++
>  drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f76fa13a12a2..050fedb4fc81 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8648,6 +8648,8 @@ enum {
>  #define GAMW_ECO_DEV_RW_IA_REG                 _MMIO(0x4080)
>  #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE      (1 << 7)
>  
> +#define GEN10_SAMPLER_MODE             _MMIO(0xE18C)
> +
>  /* IVYBRIDGE DPF */
>  #define GEN7_L3CDERRST1(slice)         _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
>  #define   GEN7_L3CDERRST1_ROW_MASK     (0x7ff << 14)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 896874278852..d7176213e3ce 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -1018,6 +1018,9 @@ static void icl_whitelist_build(struct whitelist *w)
>  {
>         /* WaAllowUMDToModifyHalfSliceChicken7:icl */
>         whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
> +
> +       /* WaAllowUMDToModifySamplerMode:icl */
> +       whitelist_reg(w, GEN10_SAMPLER_MODE);

Hmm, we need the basic subtests of gem_workarounds in BAT to have any
coverage of this code.
-Chris
Chris Wilson Oct. 30, 2018, 9:20 a.m. UTC | #2 
Quoting Chris Wilson (2018-10-30 09:12:20)
> Quoting Radhakrishna Sripada (2018-10-30 08:45:04)
> > From: Oscar Mateo <oscar.mateo@intel.com>
> > 
> > Required for Bindless samplers.
> > Userspace consumer: mesa
> > 
> > V2: Rebase
> > V3: Update commit message
> > 
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h          | 2 ++
> >  drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
> >  2 files changed, 5 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index f76fa13a12a2..050fedb4fc81 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8648,6 +8648,8 @@ enum {
> >  #define GAMW_ECO_DEV_RW_IA_REG                 _MMIO(0x4080)
> >  #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE      (1 << 7)
> >  
> > +#define GEN10_SAMPLER_MODE             _MMIO(0xE18C)
> > +
> >  /* IVYBRIDGE DPF */
> >  #define GEN7_L3CDERRST1(slice)         _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
> >  #define   GEN7_L3CDERRST1_ROW_MASK     (0x7ff << 14)
> > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> > index 896874278852..d7176213e3ce 100644
> > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > @@ -1018,6 +1018,9 @@ static void icl_whitelist_build(struct whitelist *w)
> >  {
> >         /* WaAllowUMDToModifyHalfSliceChicken7:icl */
> >         whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
> > +
> > +       /* WaAllowUMDToModifySamplerMode:icl */
> > +       whitelist_reg(w, GEN10_SAMPLER_MODE);
> 
> Hmm, we need the basic subtests of gem_workarounds in BAT to have any
> coverage of this code.

Nah, we have live_reset_whitelist() to provide basic coverage in BAT.
-Chris
Srivatsa, Anusha Oct. 31, 2018, 6:50 p.m. UTC | #3 
>-----Original Message-----
>From: Sripada, Radhakrishna
>Sent: Tuesday, October 30, 2018 1:45 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Oscar Mateo <oscar.mateo@intel.com>; Srivatsa, Anusha
><anusha.srivatsa@intel.com>; Mika Kuoppala <mika.kuoppala@linux.intel.com>;
>Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
>Subject: [PATCH v3 4/4] drm/i915/icl: WaAllowUMDToModifySamplerMode
>
>From: Oscar Mateo <oscar.mateo@intel.com>
>
>Required for Bindless samplers.
>Userspace consumer: mesa
>
>V2: Rebase
>V3: Update commit message
>
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Checked with WA database.

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h          | 2 ++
> drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
> 2 files changed, 5 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index f76fa13a12a2..050fedb4fc81 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -8648,6 +8648,8 @@ enum {
> #define GAMW_ECO_DEV_RW_IA_REG			_MMIO(0x4080)
> #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE	(1 << 7)
>
>+#define GEN10_SAMPLER_MODE		_MMIO(0xE18C)
>+
> /* IVYBRIDGE DPF */
> #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) *
>0x200) /* L3CD Error Status 1 */
> #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff << 14)
>diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
>b/drivers/gpu/drm/i915/intel_workarounds.c
>index 896874278852..d7176213e3ce 100644
>--- a/drivers/gpu/drm/i915/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/intel_workarounds.c
>@@ -1018,6 +1018,9 @@ static void icl_whitelist_build(struct whitelist *w)  {
> 	/* WaAllowUMDToModifyHalfSliceChicken7:icl */
> 	whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
>+
>+	/* WaAllowUMDToModifySamplerMode:icl */
>+	whitelist_reg(w, GEN10_SAMPLER_MODE);
> }
>
> static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
>--
>2.9.3
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f76fa13a12a2..050fedb4fc81 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8648,6 +8648,8 @@  enum {
 #define GAMW_ECO_DEV_RW_IA_REG			_MMIO(0x4080)
 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE	(1 << 7)
 
+#define GEN10_SAMPLER_MODE		_MMIO(0xE18C)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff << 14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 896874278852..d7176213e3ce 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1018,6 +1018,9 @@  static void icl_whitelist_build(struct whitelist *w)
 {
 	/* WaAllowUMDToModifyHalfSliceChicken7:icl */
 	whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
+
+	/* WaAllowUMDToModifySamplerMode:icl */
+	whitelist_reg(w, GEN10_SAMPLER_MODE);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,