| Message ID | 20181106064206.17535-4-weiyi.lu@mediatek.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Mediatek MT8183 clock and scpsys support | expand |
On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote: > > From: Owen Chen <owen.chen@mediatek.com> > > 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits, > add a variable to indicate this change and > backward-compatible. > 2. fmin: The pll freqency lower-bound is vary from 1GMhz to > 1.5Ghz, add a variable to indicate platform-dependent. > > Signed-off-by: Owen Chen <owen.chen@mediatek.com> > --- > drivers/clk/mediatek/clk-mtk.h | 2 ++ > drivers/clk/mediatek/clk-pll.c | 10 +++++++--- > 2 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h > index f83c2bbb677e..1882221fe994 100644 > --- a/drivers/clk/mediatek/clk-mtk.h > +++ b/drivers/clk/mediatek/clk-mtk.h > @@ -215,7 +215,9 @@ struct mtk_pll_data { > const struct clk_ops *ops; > u32 rst_bar_mask; > unsigned long fmax; > + unsigned long fmin; Minor nit: I'd put fmin before fmax in the structure. > int pcwbits; > + int pcwibits; > uint32_t pcw_reg; > int pcw_shift; > const struct mtk_pll_div_table *div_table; > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > index f54e4015b0b1..0ec2c62d9383 100644 > --- a/drivers/clk/mediatek/clk-pll.c > +++ b/drivers/clk/mediatek/clk-pll.c I'd add a note next to: #define INTEGER_BITS 7 to say that this is the default, and can be overridden with pcwibits. > @@ -69,11 +69,13 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, > { > int pcwbits = pll->data->pcwbits; > int pcwfbits; > + int ibits; > u64 vco; > u8 c = 0; > > /* The fractional part of the PLL divider. */ > - pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0; > + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; > + pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0; > > vco = (u64)fin * pcw; > > @@ -138,9 +140,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, > u32 freq, u32 fin) > { > - unsigned long fmin = 1000 * MHZ; > + unsigned long fmin = pll->data->fmin ? pll->data->fmin : 1000 * MHZ; I'd put parentheses around (1000 * MHZ), to avoid the need to think about precedence... > const struct mtk_pll_div_table *div_table = pll->data->div_table; > u64 _pcw; > + int ibits; > u32 val; > > if (freq > pll->data->fmax) > @@ -164,7 +167,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, > } > > /* _pcw = freq * postdiv / fin * 2^pcwfbits */ > - _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS); > + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; > + _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits); > do_div(_pcw, fin); > > *pcw = (u32)_pcw; > -- > 2.18.0 >
On Tue, 2018-11-13 at 08:18 -0800, Nicolas Boichat wrote: > On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote: > > > > From: Owen Chen <owen.chen@mediatek.com> > > > > 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits, > > add a variable to indicate this change and > > backward-compatible. > > 2. fmin: The pll freqency lower-bound is vary from 1GMhz to > > 1.5Ghz, add a variable to indicate platform-dependent. > > > > Signed-off-by: Owen Chen <owen.chen@mediatek.com> > > --- > > drivers/clk/mediatek/clk-mtk.h | 2 ++ > > drivers/clk/mediatek/clk-pll.c | 10 +++++++--- > > 2 files changed, 9 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h > > index f83c2bbb677e..1882221fe994 100644 > > --- a/drivers/clk/mediatek/clk-mtk.h > > +++ b/drivers/clk/mediatek/clk-mtk.h > > @@ -215,7 +215,9 @@ struct mtk_pll_data { > > const struct clk_ops *ops; > > u32 rst_bar_mask; > > unsigned long fmax; > > + unsigned long fmin; > > Minor nit: I'd put fmin before fmax in the structure. > OK, thanks for the suggestion. will fix in next version > > int pcwbits; > > + int pcwibits; > > uint32_t pcw_reg; > > int pcw_shift; > > const struct mtk_pll_div_table *div_table; > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > > index f54e4015b0b1..0ec2c62d9383 100644 > > --- a/drivers/clk/mediatek/clk-pll.c > > +++ b/drivers/clk/mediatek/clk-pll.c > > I'd add a note next to: > #define INTEGER_BITS 7 > to say that this is the default, and can be overridden with pcwibits. > OK, thanks for the suggestion. will add in next version > > @@ -69,11 +69,13 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, > > { > > int pcwbits = pll->data->pcwbits; > > int pcwfbits; > > + int ibits; > > u64 vco; > > u8 c = 0; > > > > /* The fractional part of the PLL divider. */ > > - pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0; > > + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; > > + pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0; > > > > vco = (u64)fin * pcw; > > > > @@ -138,9 +140,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > > static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, > > u32 freq, u32 fin) > > { > > - unsigned long fmin = 1000 * MHZ; > > + unsigned long fmin = pll->data->fmin ? pll->data->fmin : 1000 * MHZ; > > I'd put parentheses around (1000 * MHZ), to avoid the need to think > about precedence... > OK, thanks for the suggestion. will add in next version > > const struct mtk_pll_div_table *div_table = pll->data->div_table; > > u64 _pcw; > > + int ibits; > > u32 val; > > > > if (freq > pll->data->fmax) > > @@ -164,7 +167,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, > > } > > > > /* _pcw = freq * postdiv / fin * 2^pcwfbits */ > > - _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS); > > + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; > > + _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits); > > do_div(_pcw, fin); > > > > *pcw = (u32)_pcw; > > -- > > 2.18.0 > > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
Quoting Weiyi Lu (2018-11-19 19:51:20) > On Tue, 2018-11-13 at 08:18 -0800, Nicolas Boichat wrote: > > On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote: > > > @@ -138,9 +140,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > > > static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, > > > u32 freq, u32 fin) > > > { > > > - unsigned long fmin = 1000 * MHZ; > > > + unsigned long fmin = pll->data->fmin ? pll->data->fmin : 1000 * MHZ; > > > > I'd put parentheses around (1000 * MHZ), to avoid the need to think > > about precedence... > > > > OK, thanks for the suggestion. will add in next version Better style would be to not use a ternary statement for anything like this and have an if condition instead.
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index f83c2bbb677e..1882221fe994 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -215,7 +215,9 @@ struct mtk_pll_data { const struct clk_ops *ops; u32 rst_bar_mask; unsigned long fmax; + unsigned long fmin; int pcwbits; + int pcwibits; uint32_t pcw_reg; int pcw_shift; const struct mtk_pll_div_table *div_table; diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index f54e4015b0b1..0ec2c62d9383 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -69,11 +69,13 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, { int pcwbits = pll->data->pcwbits; int pcwfbits; + int ibits; u64 vco; u8 c = 0; /* The fractional part of the PLL divider. */ - pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0; + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; + pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0; vco = (u64)fin * pcw; @@ -138,9 +140,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, u32 freq, u32 fin) { - unsigned long fmin = 1000 * MHZ; + unsigned long fmin = pll->data->fmin ? pll->data->fmin : 1000 * MHZ; const struct mtk_pll_div_table *div_table = pll->data->div_table; u64 _pcw; + int ibits; u32 val; if (freq > pll->data->fmax) @@ -164,7 +167,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, } /* _pcw = freq * postdiv / fin * 2^pcwfbits */ - _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS); + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; + _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits); do_div(_pcw, fin); *pcw = (u32)_pcw;