| Message ID | 20181105185046.2802-8-aaron@os.amperecomputing.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | More fully implement ARM PMUv3 | expand |
On 5 November 2018 at 18:51, Aaron Lindsay <aaron@os.amperecomputing.com> wrote: > This commit doesn't add any supported events, but provides the framework > for adding them. We store the pm_event structs in a simple array, and > provide the mapping from the event numbers to array indexes in the > supported_event_map array. Because the value of PMCEID[01] depends upon > which events are supported at runtime, generate it dynamically. > > Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> > --- > target/arm/cpu.c | 20 +++++++++++++------- > target/arm/cpu.h | 10 ++++++++++ > target/arm/cpu64.c | 4 ---- > target/arm/helper.c | 42 ++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 65 insertions(+), 11 deletions(-) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 9e54c56379..d1c766d180 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -957,9 +957,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) > if (!cpu->has_pmu) { > unset_feature(env, ARM_FEATURE_PMU); > cpu->id_aa64dfr0 &= ~0xf00; > - } else if (!kvm_enabled()) { > - arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); > - arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); > + } > + if (arm_feature(env, ARM_FEATURE_PMU)) { > + uint64_t pmceid = get_pmceid(&cpu->env); > + cpu->pmceid0 = extract64(pmceid, 0, 32); > + cpu->pmceid1 = extract64(pmceid, 32, 32); > + > + if (!kvm_enabled()) { > + arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); > + arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); > + } > + } else { > + cpu->pmceid0 = 0x00000000; > + cpu->pmceid1 = 0x00000000; > } This now sets one of the ID registers for "we have no PMU" in the first "if (!cpu->has_pmu)" statement (id_aa64dfr0), and some of them (pmceid0, pcmeid1) in this else clause at the end. We should put them all in the same place. > > if (!arm_feature(env, ARM_FEATURE_EL2)) { > @@ -1601,8 +1611,6 @@ static void cortex_a7_initfn(Object *obj) > cpu->id_pfr0 = 0x00001131; > cpu->id_pfr1 = 0x00011011; > cpu->id_dfr0 = 0x02010555; > - cpu->pmceid0 = 0x00000000; > - cpu->pmceid1 = 0x00000000; > cpu->id_afr0 = 0x00000000; > cpu->id_mmfr0 = 0x10101105; > cpu->id_mmfr1 = 0x40000000; > @@ -1647,8 +1655,6 @@ static void cortex_a15_initfn(Object *obj) > cpu->id_pfr0 = 0x00001131; > cpu->id_pfr1 = 0x00011011; > cpu->id_dfr0 = 0x02010555; > - cpu->pmceid0 = 0x0000000; > - cpu->pmceid1 = 0x00000000; > cpu->id_afr0 = 0x00000000; > cpu->id_mmfr0 = 0x10201105; > cpu->id_mmfr1 = 0x20000000; > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 92282cd976..f991ff370e 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -991,6 +991,16 @@ void pmu_op_finish(CPUARMState *env); > void pmu_pre_el_change(ARMCPU *cpu, void *ignored); > void pmu_post_el_change(ARMCPU *cpu, void *ignored); > > +/* > + * get_pmceid > + * @env: CPUARMState > + * > + * Return the PMCEID[01] register values corresponding to the counters which > + * are supported given the current configuration (0 is low 32, 1 is high 32 > + * bits) > + */ > +uint64_t get_pmceid(CPUARMState *env); This doesn't look like the right API, because in AArch64 PMCEID0_EL0 and PMCEID1_EL0 are both 64-bit registers, so you can't fit them both into a single uint64_t. thanks -- PMM
On Nov 16 15:06, Peter Maydell wrote: > On 5 November 2018 at 18:51, Aaron Lindsay <aaron@os.amperecomputing.com> wrote: > > --- a/target/arm/cpu.c > > +++ b/target/arm/cpu.c > > @@ -957,9 +957,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) > > if (!cpu->has_pmu) { > > unset_feature(env, ARM_FEATURE_PMU); > > cpu->id_aa64dfr0 &= ~0xf00; > > - } else if (!kvm_enabled()) { > > - arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); > > - arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); > > + } > > + if (arm_feature(env, ARM_FEATURE_PMU)) { > > + uint64_t pmceid = get_pmceid(&cpu->env); > > + cpu->pmceid0 = extract64(pmceid, 0, 32); > > + cpu->pmceid1 = extract64(pmceid, 32, 32); > > + > > + if (!kvm_enabled()) { > > + arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); > > + arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); > > + } > > + } else { > > + cpu->pmceid0 = 0x00000000; > > + cpu->pmceid1 = 0x00000000; > > } > > This now sets one of the ID registers for "we have no > PMU" in the first "if (!cpu->has_pmu)" statement (id_aa64dfr0), > and some of them (pmceid0, pcmeid1) in this else clause at the > end. We should put them all in the same place. I agree that would be cleaner - I'll move the id_aa64dfr0 update to later else clause. > > +/* > > + * get_pmceid > > + * @env: CPUARMState > > + * > > + * Return the PMCEID[01] register values corresponding to the counters which > > + * are supported given the current configuration (0 is low 32, 1 is high 32 > > + * bits) > > + */ > > +uint64_t get_pmceid(CPUARMState *env); > > This doesn't look like the right API, because in AArch64 > PMCEID0_EL0 and PMCEID1_EL0 are both 64-bit registers, > so you can't fit them both into a single uint64_t. Heh, I think I started working on this long enough ago that I was using a copy of the ARMv8.0 ARM - before the statistical profiling extensions were announced. I believe those are the only currently-defined common events >= 0x4000, so they're the only bits defined in the upper 32 bits of PMCEID[01]. Now that I look at it, pmceid[01] are currently only defined as uint32_t, and we don't have PMCEID[23] for the high bits for AArch32. Perhaps that should be a separate patch. At any rate, I'll plan to update this the following signature for the next version, where `which` is [01] for which PMCEID is being requested. For now I'll probably just put a comment about not supporting the 0x40xx events, since I don't know that coming up with a sparse array is worth it, but the signature will be appropriate if we add support later: uint64_t get_pmceid(CPUARMState *env, unsigned which); -Aaron
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9e54c56379..d1c766d180 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -957,9 +957,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (!cpu->has_pmu) { unset_feature(env, ARM_FEATURE_PMU); cpu->id_aa64dfr0 &= ~0xf00; - } else if (!kvm_enabled()) { - arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); - arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); + } + if (arm_feature(env, ARM_FEATURE_PMU)) { + uint64_t pmceid = get_pmceid(&cpu->env); + cpu->pmceid0 = extract64(pmceid, 0, 32); + cpu->pmceid1 = extract64(pmceid, 32, 32); + + if (!kvm_enabled()) { + arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); + arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); + } + } else { + cpu->pmceid0 = 0x00000000; + cpu->pmceid1 = 0x00000000; } if (!arm_feature(env, ARM_FEATURE_EL2)) { @@ -1601,8 +1611,6 @@ static void cortex_a7_initfn(Object *obj) cpu->id_pfr0 = 0x00001131; cpu->id_pfr1 = 0x00011011; cpu->id_dfr0 = 0x02010555; - cpu->pmceid0 = 0x00000000; - cpu->pmceid1 = 0x00000000; cpu->id_afr0 = 0x00000000; cpu->id_mmfr0 = 0x10101105; cpu->id_mmfr1 = 0x40000000; @@ -1647,8 +1655,6 @@ static void cortex_a15_initfn(Object *obj) cpu->id_pfr0 = 0x00001131; cpu->id_pfr1 = 0x00011011; cpu->id_dfr0 = 0x02010555; - cpu->pmceid0 = 0x0000000; - cpu->pmceid1 = 0x00000000; cpu->id_afr0 = 0x00000000; cpu->id_mmfr0 = 0x10201105; cpu->id_mmfr1 = 0x20000000; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 92282cd976..f991ff370e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -991,6 +991,16 @@ void pmu_op_finish(CPUARMState *env); void pmu_pre_el_change(ARMCPU *cpu, void *ignored); void pmu_post_el_change(ARMCPU *cpu, void *ignored); +/* + * get_pmceid + * @env: CPUARMState + * + * Return the PMCEID[01] register values corresponding to the counters which + * are supported given the current configuration (0 is low 32, 1 is high 32 + * bits) + */ +uint64_t get_pmceid(CPUARMState *env); + /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants * for both old and new bit meanings. Code which tests against those diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 873f059bf2..a1aad772fa 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -138,8 +138,6 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar6 = 0; cpu->isar.id_aa64pfr0 = 0x00002222; cpu->id_aa64dfr0 = 0x10305106; - cpu->pmceid0 = 0x00000000; - cpu->pmceid1 = 0x00000000; cpu->isar.id_aa64isar0 = 0x00011120; cpu->id_aa64mmfr0 = 0x00001124; cpu->dbgdidr = 0x3516d000; @@ -246,8 +244,6 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar5 = 0x00011121; cpu->isar.id_aa64pfr0 = 0x00002222; cpu->id_aa64dfr0 = 0x10305106; - cpu->pmceid0 = 0x00000000; - cpu->pmceid1 = 0x00000000; cpu->isar.id_aa64isar0 = 0x00011120; cpu->id_aa64mmfr0 = 0x00001124; cpu->dbgdidr = 0x3516d000; diff --git a/target/arm/helper.c b/target/arm/helper.c index 6724d97346..b9d8441497 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1009,6 +1009,48 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); } +typedef struct pm_event { + uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ + /* If the event is supported on this CPU (used to generate PMCEID[01]) */ + bool (*supported)(CPUARMState *); + /* + * Retrieve the current count of the underlying event. The programmed + * counters hold a difference from the return value from this function + */ + uint64_t (*get_count)(CPUARMState *); +} pm_event; + +static const pm_event pm_events[] = { +}; +#define MAX_EVENT_ID 0x0 +#define UNSUPPORTED_EVENT UINT16_MAX +static uint16_t supported_event_map[MAX_EVENT_ID + 1]; + +/* + * Called upon initialization to build PMCEID0 (low 32 bits) and PMCEID1 (high + * 32). We also use it to build a map of ARM event numbers to indices in + * our pm_events array. + */ +uint64_t get_pmceid(CPUARMState *env) +{ + uint64_t pmceid = 0; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) { + supported_event_map[i] = UNSUPPORTED_EVENT; + } + + for (i = 0; i < ARRAY_SIZE(pm_events); i++) { + const pm_event *cnt = &pm_events[i]; + assert(cnt->number <= MAX_EVENT_ID); + if (cnt->supported(env)) { + pmceid |= (1 << cnt->number); + supported_event_map[cnt->number] = i; + } + } + return pmceid; +} + static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) {
This commit doesn't add any supported events, but provides the framework for adding them. We store the pm_event structs in a simple array, and provide the mapping from the event numbers to array indexes in the supported_event_map array. Because the value of PMCEID[01] depends upon which events are supported at runtime, generate it dynamically. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> --- target/arm/cpu.c | 20 +++++++++++++------- target/arm/cpu.h | 10 ++++++++++ target/arm/cpu64.c | 4 ---- target/arm/helper.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 65 insertions(+), 11 deletions(-)