Message ID | 20181116010412.23967-8-jarkko.sakkinen@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v17,01/23] x86/sgx: Update MAINTAINERS | expand |
On 11/15/18 5:01 PM, Jarkko Sakkinen wrote: > The SGX bit is set in the #PF error code if and only if the fault is > detected by the Enclave Page Cache Map (EPCM), a hardware-managed > table that enforces the paging permissions defined by the enclave, > e.g. to prevent the kernel from changing the permissions of an > enclave's page(s). This should probably also mention that, despite being a page fault, X86_PF_SGX has nothing to do with paging itself.
On Fri, Nov 16, 2018 at 03:33:35PM -0800, Dave Hansen wrote: > On 11/15/18 5:01 PM, Jarkko Sakkinen wrote: > > The SGX bit is set in the #PF error code if and only if the fault is > > detected by the Enclave Page Cache Map (EPCM), a hardware-managed > > table that enforces the paging permissions defined by the enclave, > > e.g. to prevent the kernel from changing the permissions of an > > enclave's page(s). > > This should probably also mention that, despite being a page fault, > X86_PF_SGX has nothing to do with paging itself. A valid point. /Jarkko
diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h index 3de69330e6c5..165c93dd700e 100644 --- a/arch/x86/include/asm/traps.h +++ b/arch/x86/include/asm/traps.h @@ -162,5 +162,6 @@ enum x86_pf_error_code { X86_PF_RSVD = 1 << 3, X86_PF_INSTR = 1 << 4, X86_PF_PK = 1 << 5, + X86_PF_SGX = 1 << 15, }; #endif /* _ASM_X86_TRAPS_H */