| Message ID | 20181127003710.18618-9-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/9] drm/i915: Disable PSR in Apple panels | expand |
On Mon, Nov 26, 2018 at 04:37:10PM -0800, José Roberto de Souza wrote: > Our frontbuffer tracking improved over the years + the WA #0884 > helped us keep PSR2 enabled while triggering screen updates when > necessary so this FIXME is not valid anymore. > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/intel_psr.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index 6fd793fec5e9..a1bde8bbd85b 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -490,9 +490,6 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > /* Avoid deep sleep as much as possible to avoid PSR2 idle state */ > val |= EDP_PSR2_IDLE_FRAMES_TO_DEEP_SLEEP(15); > > - /* FIXME: selective update is probably totally broken because it doesn't > - * mesh at all with our frontbuffer tracking. And the hw alone isn't > - * good enough. */ > val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > val |= EDP_Y_COORDINATE_ENABLE; > -- > 2.19.2 >
On Thu, 2018-11-29 at 15:11 -0800, Rodrigo Vivi wrote: > On Mon, Nov 26, 2018 at 04:37:10PM -0800, José Roberto de Souza > wrote: > > Our frontbuffer tracking improved over the years + the WA #0884 > > helped us keep PSR2 enabled while triggering screen updates when > > necessary so this FIXME is not valid anymore. > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > > --- > > drivers/gpu/drm/i915/intel_psr.c | 3 --- > > 1 file changed, 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index 6fd793fec5e9..a1bde8bbd85b 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -490,9 +490,6 @@ static void hsw_activate_psr2(struct intel_dp > > *intel_dp) > > /* Avoid deep sleep as much as possible to avoid PSR2 idle > > state */ > > val |= EDP_PSR2_IDLE_FRAMES_TO_DEEP_SLEEP(15); > > > > - /* FIXME: selective update is probably totally broken because > > it doesn't > > - * mesh at all with our frontbuffer tracking. And the hw alone > > isn't > > - * good enough. */ > > val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; > > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > > val |= EDP_Y_COORDINATE_ENABLE; > > -- > > 2.19.2 > >
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 6fd793fec5e9..a1bde8bbd85b 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -490,9 +490,6 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) /* Avoid deep sleep as much as possible to avoid PSR2 idle state */ val |= EDP_PSR2_IDLE_FRAMES_TO_DEEP_SLEEP(15); - /* FIXME: selective update is probably totally broken because it doesn't - * mesh at all with our frontbuffer tracking. And the hw alone isn't - * good enough. */ val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) val |= EDP_Y_COORDINATE_ENABLE;
Our frontbuffer tracking improved over the years + the WA #0884 helped us keep PSR2 enabled while triggering screen updates when necessary so this FIXME is not valid anymore. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/intel_psr.c | 3 --- 1 file changed, 3 deletions(-)