| Message ID | 1543618681-15255-1-git-send-email-clinton.a.taylor@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/icl: combo port vswing programming changes per BSPEC | expand |
On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.taylor@intel.com wrote: > From: Clint Taylor <clinton.a.taylor@intel.com> > > In August 2018 the BSPEC changed the ICL port programming sequence to > closely resemble earlier gen programming sequence. > > BSpec: 21257 > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 + > drivers/gpu/drm/i915/intel_ddi.c | 223 +++++++++++++---------------------- > drivers/gpu/drm/i915/intel_display.c | 3 - > 3 files changed, 86 insertions(+), 144 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index d3ef979..e632e99 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1866,6 +1866,10 @@ enum i915_power_well_id { > > #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7)) > #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7)) > +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port)) > +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port)) > +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port)) > +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port)) > #define N_SCALAR(x) ((x) << 24) > #define N_SCALAR_MASK (0x7F << 24) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 61d7145..219464e9 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -493,103 +493,63 @@ struct cnl_ddi_buf_trans { > { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ > }; > > -struct icl_combo_phy_ddi_buf_trans { > - u32 dw2_swing_select; > - u32 dw2_swing_scalar; > - u32 dw4_scaling; > -}; > - > -/* Voltage Swing Programming for VccIO 0.85V for DP */ > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = { > - /* Voltage mV db */ > - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ > - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ > - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ > - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ > - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */ > - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */ > - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */ > - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */ > - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */ > - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ > -}; > - > -/* FIXME - After table is updated in Bspec */ > -/* Voltage Swing Programming for VccIO 0.85V for eDP */ > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = { > - /* Voltage mV db */ > - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ > - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ > - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ > - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ > +/* icl_combo_phy_ddi_translations */ > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = { > + /* NT mV Trans mV db */ > + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ > + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ > + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ > + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ > + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ > + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ > + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */ > + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ > }; > > -/* Voltage Swing Programming for VccIO 0.95V for DP */ > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = { > - /* Voltage mV db */ > - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ > - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ > - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ > - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ > - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */ > - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */ > - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */ > - { 0x5, 0x76, 0x0018 }, /* 800 0.0 */ > - { 0x5, 0x76, 0x3015 }, /* 800 3.5 */ > - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = { > + /* NT mV Trans mV db */ > + { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ > + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ > + { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ > + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ > + { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ > + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > + { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > + { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > }; > > -/* FIXME - After table is updated in Bspec */ > -/* Voltage Swing Programming for VccIO 0.95V for eDP */ > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = { > - /* Voltage mV db */ > - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ > - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ > - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ > - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { > + /* NT mV Trans mV db */ > + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ > + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ > + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ > + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ > + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ > + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ > + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ > + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ > }; > > -/* Voltage Swing Programming for VccIO 1.05V for DP */ > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = { > - /* Voltage mV db */ > - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ > - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ > - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ > - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ > - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */ > - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */ > - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */ > - { 0x5, 0x71, 0x0018 }, /* 800 0.0 */ > - { 0x5, 0x71, 0x3015 }, /* 800 3.5 */ > - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { > + /* NT mV Trans mV db */ > + { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ > + { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ > + { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ > + { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ > + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ > + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ > }; > > -/* FIXME - After table is updated in Bspec */ > -/* Voltage Swing Programming for VccIO 1.05V for eDP */ > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = { > - /* Voltage mV db */ > - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ > - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ > - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ > - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = { > + /* NT mV Trans mV db */ > + { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ > }; > > struct icl_mg_phy_ddi_buf_trans { > @@ -870,43 +830,27 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) > } > } > > -static const struct icl_combo_phy_ddi_buf_trans * > +static const struct cnl_ddi_buf_trans * > icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port, > int type, int *n_entries) > { > - u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK; > > if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { > - switch (voltage) { > - case VOLTAGE_INFO_0_85V: > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V); > - return icl_combo_phy_ddi_translations_edp_0_85V; > - case VOLTAGE_INFO_0_95V: > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V); > - return icl_combo_phy_ddi_translations_edp_0_95V; > - case VOLTAGE_INFO_1_05V: > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V); > - return icl_combo_phy_ddi_translations_edp_1_05V; > - default: > - MISSING_CASE(voltage); > - return NULL; > - } > - } else { > - switch (voltage) { > - case VOLTAGE_INFO_0_85V: > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V); > - return icl_combo_phy_ddi_translations_dp_hdmi_0_85V; > - case VOLTAGE_INFO_0_95V: > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V); > - return icl_combo_phy_ddi_translations_dp_hdmi_0_95V; > - case VOLTAGE_INFO_1_05V: > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V); > - return icl_combo_phy_ddi_translations_dp_hdmi_1_05V; > - default: > - MISSING_CASE(voltage); > - return NULL; > - } > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing); > + return icl_combo_phy_ddi_translations_edp_lowswing; > + } else if (type == INTEL_OUTPUT_EDP) { > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); > + return icl_combo_phy_ddi_translations_edp_hbr3; > + } else if ((type == INTEL_OUTPUT_DP) || (type == INTEL_OUTPUT_DDI) || > + (type == INTEL_OUTPUT_DP_MST)) { > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp); > + return icl_combo_phy_ddi_translations_dp; > + } else if (type == INTEL_OUTPUT_HDMI) { > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); > + return icl_combo_phy_ddi_translations_hdmi; > } > + > + return NULL; > } > > static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) > @@ -2463,7 +2407,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, > static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > u32 level, enum port port, int type) > { > - const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL; > + const struct cnl_ddi_buf_trans *ddi_translations = NULL; > u32 n_entries, val; > int ln; > > @@ -2477,34 +2421,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > level = n_entries - 1; > } > > - /* Set PORT_TX_DW5 Rterm Sel to 110b. */ > + /* Set PORT_TX_DW5 */ > val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > - val &= ~RTERM_SELECT_MASK; > + val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | > + TAP2_DISABLE | TAP3_DISABLE); > + val |= SCALING_MODE_SEL(0x2); > val |= RTERM_SELECT(0x6); > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); > - > - /* Program PORT_TX_DW5 */ > - val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > - /* Set DisableTap2 and DisableTap3 if MIPI DSI > - * Clear DisableTap2 and DisableTap3 for all other Ports > - */ > - if (type == INTEL_OUTPUT_DSI) { > - val |= TAP2_DISABLE; > - val |= TAP3_DISABLE; > - } else { > - val &= ~TAP2_DISABLE; > - val &= ~TAP3_DISABLE; > - } > + val |= TAP3_DISABLE; > I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); > > /* Program PORT_TX_DW2 */ > val = I915_READ(ICL_PORT_TX_DW2_LN0(port)); > val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | > RCOMP_SCALAR_MASK); > - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select); > - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select); > + val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); > + val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); > /* Program Rcomp scalar for every table entry */ > - val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar); > + val |= RCOMP_SCALAR(0x98); > I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val); > > /* Program PORT_TX_DW4 */ > @@ -2513,9 +2446,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln)); > val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | > CURSOR_COEFF_MASK); > - val |= ddi_translations[level].dw4_scaling; > + val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); > + val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); > + val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); > I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val); > } > + > + /* Program PORT_TX_DW7 */ > + val = I915_READ(ICL_PORT_TX_DW7_LN0(port)); > + val &= ~N_SCALAR_MASK; > + val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); > + I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val); > } > > static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 789f647bd..6c125ae 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -15435,9 +15435,6 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) > > /* notify opregion of the sanitized encoder state */ > intel_opregion_notify_encoder(encoder, connector && has_active_crtc); > - > - if (INTEL_GEN(dev_priv) >= 11) > - icl_sanitize_encoder_pll_mapping(encoder); This looks unrelated/not explained in the commit message. The port clocking programming looks still the same, so I don't understand why we wouldn't need the above. > } > > void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) > -- > 1.9.1 >
On 11/30/2018 03:15 PM, Imre Deak wrote: > On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.taylor@intel.com wrote: >> From: Clint Taylor <clinton.a.taylor@intel.com> >> >> In August 2018 the BSPEC changed the ICL port programming sequence to >> closely resemble earlier gen programming sequence. >> >> BSpec: 21257 >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> >> Cc: Imre Deak <imre.deak@intel.com> >> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> >> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> >> --- >> drivers/gpu/drm/i915/i915_reg.h | 4 + >> drivers/gpu/drm/i915/intel_ddi.c | 223 +++++++++++++---------------------- >> drivers/gpu/drm/i915/intel_display.c | 3 - >> 3 files changed, 86 insertions(+), 144 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index d3ef979..e632e99 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -1866,6 +1866,10 @@ enum i915_power_well_id { >> >> #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7)) >> #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7)) >> +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port)) >> +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port)) >> +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port)) >> +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port)) >> #define N_SCALAR(x) ((x) << 24) >> #define N_SCALAR_MASK (0x7F << 24) >> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c >> index 61d7145..219464e9 100644 >> --- a/drivers/gpu/drm/i915/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/intel_ddi.c >> @@ -493,103 +493,63 @@ struct cnl_ddi_buf_trans { >> { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ >> }; >> >> -struct icl_combo_phy_ddi_buf_trans { >> - u32 dw2_swing_select; >> - u32 dw2_swing_scalar; >> - u32 dw4_scaling; >> -}; >> - >> -/* Voltage Swing Programming for VccIO 0.85V for DP */ >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = { >> - /* Voltage mV db */ >> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ >> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ >> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ >> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ >> - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */ >> - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */ >> - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */ >> - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */ >> - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */ >> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ >> -}; >> - >> -/* FIXME - After table is updated in Bspec */ >> -/* Voltage Swing Programming for VccIO 0.85V for eDP */ >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = { >> - /* Voltage mV db */ >> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ >> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ >> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ >> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ >> +/* icl_combo_phy_ddi_translations */ >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = { >> + /* NT mV Trans mV db */ >> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ >> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ >> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ >> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ >> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ >> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ >> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ >> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */ >> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ >> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ >> }; >> >> -/* Voltage Swing Programming for VccIO 0.95V for DP */ >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = { >> - /* Voltage mV db */ >> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ >> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ >> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ >> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ >> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */ >> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */ >> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */ >> - { 0x5, 0x76, 0x0018 }, /* 800 0.0 */ >> - { 0x5, 0x76, 0x3015 }, /* 800 3.5 */ >> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = { >> + /* NT mV Trans mV db */ >> + { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ >> + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ >> + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ >> + { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ >> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ >> + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ >> + { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ >> + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ >> + { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ >> + { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ >> }; >> >> -/* FIXME - After table is updated in Bspec */ >> -/* Voltage Swing Programming for VccIO 0.95V for eDP */ >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = { >> - /* Voltage mV db */ >> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ >> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ >> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ >> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { >> + /* NT mV Trans mV db */ >> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ >> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ >> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ >> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ >> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ >> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ >> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ >> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ >> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ >> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ >> }; >> >> -/* Voltage Swing Programming for VccIO 1.05V for DP */ >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = { >> - /* Voltage mV db */ >> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ >> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ >> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ >> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ >> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */ >> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */ >> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */ >> - { 0x5, 0x71, 0x0018 }, /* 800 0.0 */ >> - { 0x5, 0x71, 0x3015 }, /* 800 3.5 */ >> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { >> + /* NT mV Trans mV db */ >> + { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ >> + { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ >> + { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ >> + { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ >> + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ >> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ >> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ >> }; >> >> -/* FIXME - After table is updated in Bspec */ >> -/* Voltage Swing Programming for VccIO 1.05V for eDP */ >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = { >> - /* Voltage mV db */ >> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ >> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ >> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ >> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = { >> + /* NT mV Trans mV db */ >> + { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ >> }; >> >> struct icl_mg_phy_ddi_buf_trans { >> @@ -870,43 +830,27 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) >> } >> } >> >> -static const struct icl_combo_phy_ddi_buf_trans * >> +static const struct cnl_ddi_buf_trans * >> icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port, >> int type, int *n_entries) >> { >> - u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK; >> >> if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { >> - switch (voltage) { >> - case VOLTAGE_INFO_0_85V: >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V); >> - return icl_combo_phy_ddi_translations_edp_0_85V; >> - case VOLTAGE_INFO_0_95V: >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V); >> - return icl_combo_phy_ddi_translations_edp_0_95V; >> - case VOLTAGE_INFO_1_05V: >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V); >> - return icl_combo_phy_ddi_translations_edp_1_05V; >> - default: >> - MISSING_CASE(voltage); >> - return NULL; >> - } >> - } else { >> - switch (voltage) { >> - case VOLTAGE_INFO_0_85V: >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V); >> - return icl_combo_phy_ddi_translations_dp_hdmi_0_85V; >> - case VOLTAGE_INFO_0_95V: >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V); >> - return icl_combo_phy_ddi_translations_dp_hdmi_0_95V; >> - case VOLTAGE_INFO_1_05V: >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V); >> - return icl_combo_phy_ddi_translations_dp_hdmi_1_05V; >> - default: >> - MISSING_CASE(voltage); >> - return NULL; >> - } >> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing); >> + return icl_combo_phy_ddi_translations_edp_lowswing; >> + } else if (type == INTEL_OUTPUT_EDP) { >> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); >> + return icl_combo_phy_ddi_translations_edp_hbr3; >> + } else if ((type == INTEL_OUTPUT_DP) || (type == INTEL_OUTPUT_DDI) || >> + (type == INTEL_OUTPUT_DP_MST)) { >> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp); >> + return icl_combo_phy_ddi_translations_dp; >> + } else if (type == INTEL_OUTPUT_HDMI) { >> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); >> + return icl_combo_phy_ddi_translations_hdmi; >> } >> + >> + return NULL; >> } >> >> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) >> @@ -2463,7 +2407,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, >> static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, >> u32 level, enum port port, int type) >> { >> - const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL; >> + const struct cnl_ddi_buf_trans *ddi_translations = NULL; >> u32 n_entries, val; >> int ln; >> >> @@ -2477,34 +2421,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, >> level = n_entries - 1; >> } >> >> - /* Set PORT_TX_DW5 Rterm Sel to 110b. */ >> + /* Set PORT_TX_DW5 */ >> val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); >> - val &= ~RTERM_SELECT_MASK; >> + val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | >> + TAP2_DISABLE | TAP3_DISABLE); >> + val |= SCALING_MODE_SEL(0x2); >> val |= RTERM_SELECT(0x6); >> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); >> - >> - /* Program PORT_TX_DW5 */ >> - val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); >> - /* Set DisableTap2 and DisableTap3 if MIPI DSI >> - * Clear DisableTap2 and DisableTap3 for all other Ports >> - */ >> - if (type == INTEL_OUTPUT_DSI) { >> - val |= TAP2_DISABLE; >> - val |= TAP3_DISABLE; >> - } else { >> - val &= ~TAP2_DISABLE; >> - val &= ~TAP3_DISABLE; >> - } >> + val |= TAP3_DISABLE; >> I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); >> >> /* Program PORT_TX_DW2 */ >> val = I915_READ(ICL_PORT_TX_DW2_LN0(port)); >> val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | >> RCOMP_SCALAR_MASK); >> - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select); >> - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select); >> + val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); >> + val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); >> /* Program Rcomp scalar for every table entry */ >> - val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar); >> + val |= RCOMP_SCALAR(0x98); >> I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val); >> >> /* Program PORT_TX_DW4 */ >> @@ -2513,9 +2446,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, >> val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln)); >> val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | >> CURSOR_COEFF_MASK); >> - val |= ddi_translations[level].dw4_scaling; >> + val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); >> + val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); >> + val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); >> I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val); >> } >> + >> + /* Program PORT_TX_DW7 */ >> + val = I915_READ(ICL_PORT_TX_DW7_LN0(port)); >> + val &= ~N_SCALAR_MASK; >> + val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); >> + I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val); >> } >> >> static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >> index 789f647bd..6c125ae 100644 >> --- a/drivers/gpu/drm/i915/intel_display.c >> +++ b/drivers/gpu/drm/i915/intel_display.c >> @@ -15435,9 +15435,6 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) >> >> /* notify opregion of the sanitized encoder state */ >> intel_opregion_notify_encoder(encoder, connector && has_active_crtc); >> - >> - if (INTEL_GEN(dev_priv) >= 11) >> - icl_sanitize_encoder_pll_mapping(encoder); > This looks unrelated/not explained in the commit message. The port > clocking programming looks still the same, so I don't understand why we > wouldn't need the above. Oops, forgot to remove this debug code. -Clint >> } >> >> void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) >> -- >> 1.9.1 >>
On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.taylor@intel.com wrote: > From: Clint Taylor <clinton.a.taylor@intel.com> > > In August 2018 the BSPEC changed the ICL port programming sequence to > closely resemble earlier gen programming sequence. > > BSpec: 21257 > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 + > drivers/gpu/drm/i915/intel_ddi.c | 223 +++++++++++++---------------------- > drivers/gpu/drm/i915/intel_display.c | 3 - > 3 files changed, 86 insertions(+), 144 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index d3ef979..e632e99 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1866,6 +1866,10 @@ enum i915_power_well_id { > > #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7)) > #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7)) > +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port)) > +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port)) > +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port)) > +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port)) > #define N_SCALAR(x) ((x) << 24) > #define N_SCALAR_MASK (0x7F << 24) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 61d7145..219464e9 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -493,103 +493,63 @@ struct cnl_ddi_buf_trans { > { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ > }; > > -struct icl_combo_phy_ddi_buf_trans { > - u32 dw2_swing_select; > - u32 dw2_swing_scalar; > - u32 dw4_scaling; > -}; > - > -/* Voltage Swing Programming for VccIO 0.85V for DP */ > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = { > - /* Voltage mV db */ > - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ > - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ > - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ > - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ > - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */ > - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */ > - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */ > - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */ > - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */ > - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ > -}; > - > -/* FIXME - After table is updated in Bspec */ > -/* Voltage Swing Programming for VccIO 0.85V for eDP */ > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = { > - /* Voltage mV db */ > - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ > - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ > - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ > - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ > +/* icl_combo_phy_ddi_translations */ > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = { > + /* NT mV Trans mV db */ > + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ > + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ > + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ > + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ > + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ > + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ > + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */ > + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ > }; > > -/* Voltage Swing Programming for VccIO 0.95V for DP */ > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = { > - /* Voltage mV db */ > - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ > - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ > - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ > - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ > - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */ > - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */ > - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */ > - { 0x5, 0x76, 0x0018 }, /* 800 0.0 */ > - { 0x5, 0x76, 0x3015 }, /* 800 3.5 */ > - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = { > + /* NT mV Trans mV db */ > + { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ > + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ > + { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ > + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ > + { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ > + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > + { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > + { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > }; > > -/* FIXME - After table is updated in Bspec */ > -/* Voltage Swing Programming for VccIO 0.95V for eDP */ > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = { > - /* Voltage mV db */ > - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ > - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ > - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ > - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { > + /* NT mV Trans mV db */ > + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ > + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ > + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ > + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ > + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ > + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ > + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ > + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ > }; > > -/* Voltage Swing Programming for VccIO 1.05V for DP */ > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = { > - /* Voltage mV db */ > - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ > - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ > - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ > - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ > - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */ > - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */ > - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */ > - { 0x5, 0x71, 0x0018 }, /* 800 0.0 */ > - { 0x5, 0x71, 0x3015 }, /* 800 3.5 */ > - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { > + /* NT mV Trans mV db */ > + { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ > + { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ > + { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ > + { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ > + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ > + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ > }; > > -/* FIXME - After table is updated in Bspec */ > -/* Voltage Swing Programming for VccIO 1.05V for eDP */ > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = { > - /* Voltage mV db */ > - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ > - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ > - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ > - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ > - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ > - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = { > + /* NT mV Trans mV db */ > + { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ > }; > > struct icl_mg_phy_ddi_buf_trans { > @@ -870,43 +830,27 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) > } > } > > -static const struct icl_combo_phy_ddi_buf_trans * > +static const struct cnl_ddi_buf_trans * > icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port, > int type, int *n_entries) > { > - u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK; > > if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { > - switch (voltage) { > - case VOLTAGE_INFO_0_85V: > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V); > - return icl_combo_phy_ddi_translations_edp_0_85V; > - case VOLTAGE_INFO_0_95V: > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V); > - return icl_combo_phy_ddi_translations_edp_0_95V; > - case VOLTAGE_INFO_1_05V: > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V); > - return icl_combo_phy_ddi_translations_edp_1_05V; > - default: > - MISSING_CASE(voltage); > - return NULL; > - } > - } else { > - switch (voltage) { > - case VOLTAGE_INFO_0_85V: > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V); > - return icl_combo_phy_ddi_translations_dp_hdmi_0_85V; > - case VOLTAGE_INFO_0_95V: > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V); > - return icl_combo_phy_ddi_translations_dp_hdmi_0_95V; > - case VOLTAGE_INFO_1_05V: > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V); > - return icl_combo_phy_ddi_translations_dp_hdmi_1_05V; > - default: > - MISSING_CASE(voltage); > - return NULL; > - } > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing); > + return icl_combo_phy_ddi_translations_edp_lowswing; > + } else if (type == INTEL_OUTPUT_EDP) { > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); > + return icl_combo_phy_ddi_translations_edp_hbr3; > + } else if ((type == INTEL_OUTPUT_DP) || (type == INTEL_OUTPUT_DDI) || > + (type == INTEL_OUTPUT_DP_MST)) { I would move the hdmi case first to match how most other platforms do it, and to eliminate this complicated DP check. > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp); > + return icl_combo_phy_ddi_translations_dp; > + } else if (type == INTEL_OUTPUT_HDMI) { > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); > + return icl_combo_phy_ddi_translations_hdmi; > } > + > + return NULL; > } > > static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) > @@ -2463,7 +2407,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, > static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > u32 level, enum port port, int type) > { > - const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL; > + const struct cnl_ddi_buf_trans *ddi_translations = NULL; > u32 n_entries, val; > int ln; > > @@ -2477,34 +2421,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > level = n_entries - 1; > } > > - /* Set PORT_TX_DW5 Rterm Sel to 110b. */ > + /* Set PORT_TX_DW5 */ > val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > - val &= ~RTERM_SELECT_MASK; > + val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | > + TAP2_DISABLE | TAP3_DISABLE); > + val |= SCALING_MODE_SEL(0x2); > val |= RTERM_SELECT(0x6); > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); > - > - /* Program PORT_TX_DW5 */ > - val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > - /* Set DisableTap2 and DisableTap3 if MIPI DSI > - * Clear DisableTap2 and DisableTap3 for all other Ports > - */ > - if (type == INTEL_OUTPUT_DSI) { > - val |= TAP2_DISABLE; > - val |= TAP3_DISABLE; > - } else { > - val &= ~TAP2_DISABLE; > - val &= ~TAP3_DISABLE; > - } > + val |= TAP3_DISABLE; > I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); > > /* Program PORT_TX_DW2 */ > val = I915_READ(ICL_PORT_TX_DW2_LN0(port)); > val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | > RCOMP_SCALAR_MASK); > - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select); > - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select); > + val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); > + val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); > /* Program Rcomp scalar for every table entry */ > - val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar); > + val |= RCOMP_SCALAR(0x98); > I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val); > > /* Program PORT_TX_DW4 */ > @@ -2513,9 +2446,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln)); > val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | > CURSOR_COEFF_MASK); > - val |= ddi_translations[level].dw4_scaling; > + val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); > + val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); > + val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); > I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val); > } > + > + /* Program PORT_TX_DW7 */ The comment is redundant. > + val = I915_READ(ICL_PORT_TX_DW7_LN0(port)); > + val &= ~N_SCALAR_MASK; > + val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); > + I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val); > } > > static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 789f647bd..6c125ae 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -15435,9 +15435,6 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) > > /* notify opregion of the sanitized encoder state */ > intel_opregion_notify_encoder(encoder, connector && has_active_crtc); > - > - if (INTEL_GEN(dev_priv) >= 11) > - icl_sanitize_encoder_pll_mapping(encoder); > } > > void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) > -- > 1.9.1
On 12/03/2018 04:19 AM, Ville Syrjälä wrote: > On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.taylor@intel.com wrote: >> From: Clint Taylor <clinton.a.taylor@intel.com> >> >> In August 2018 the BSPEC changed the ICL port programming sequence to >> closely resemble earlier gen programming sequence. >> >> BSpec: 21257 >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> >> Cc: Imre Deak <imre.deak@intel.com> >> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> >> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> >> --- >> drivers/gpu/drm/i915/i915_reg.h | 4 + >> drivers/gpu/drm/i915/intel_ddi.c | 223 +++++++++++++---------------------- >> drivers/gpu/drm/i915/intel_display.c | 3 - >> 3 files changed, 86 insertions(+), 144 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index d3ef979..e632e99 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -1866,6 +1866,10 @@ enum i915_power_well_id { >> >> #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7)) >> #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7)) >> +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port)) >> +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port)) >> +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port)) >> +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port)) >> #define N_SCALAR(x) ((x) << 24) >> #define N_SCALAR_MASK (0x7F << 24) >> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c >> index 61d7145..219464e9 100644 >> --- a/drivers/gpu/drm/i915/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/intel_ddi.c >> @@ -493,103 +493,63 @@ struct cnl_ddi_buf_trans { >> { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ >> }; >> >> -struct icl_combo_phy_ddi_buf_trans { >> - u32 dw2_swing_select; >> - u32 dw2_swing_scalar; >> - u32 dw4_scaling; >> -}; >> - >> -/* Voltage Swing Programming for VccIO 0.85V for DP */ >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = { >> - /* Voltage mV db */ >> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ >> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ >> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ >> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ >> - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */ >> - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */ >> - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */ >> - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */ >> - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */ >> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ >> -}; >> - >> -/* FIXME - After table is updated in Bspec */ >> -/* Voltage Swing Programming for VccIO 0.85V for eDP */ >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = { >> - /* Voltage mV db */ >> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ >> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ >> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ >> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ >> +/* icl_combo_phy_ddi_translations */ >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = { >> + /* NT mV Trans mV db */ >> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ >> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ >> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ >> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ >> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ >> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ >> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ >> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */ >> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ >> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ >> }; >> >> -/* Voltage Swing Programming for VccIO 0.95V for DP */ >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = { >> - /* Voltage mV db */ >> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ >> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ >> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ >> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ >> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */ >> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */ >> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */ >> - { 0x5, 0x76, 0x0018 }, /* 800 0.0 */ >> - { 0x5, 0x76, 0x3015 }, /* 800 3.5 */ >> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = { >> + /* NT mV Trans mV db */ >> + { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ >> + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ >> + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ >> + { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ >> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ >> + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ >> + { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ >> + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ >> + { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ >> + { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ >> }; >> >> -/* FIXME - After table is updated in Bspec */ >> -/* Voltage Swing Programming for VccIO 0.95V for eDP */ >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = { >> - /* Voltage mV db */ >> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ >> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ >> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ >> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { >> + /* NT mV Trans mV db */ >> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ >> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ >> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ >> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ >> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ >> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ >> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ >> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ >> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ >> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ >> }; >> >> -/* Voltage Swing Programming for VccIO 1.05V for DP */ >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = { >> - /* Voltage mV db */ >> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ >> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ >> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ >> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ >> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */ >> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */ >> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */ >> - { 0x5, 0x71, 0x0018 }, /* 800 0.0 */ >> - { 0x5, 0x71, 0x3015 }, /* 800 3.5 */ >> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { >> + /* NT mV Trans mV db */ >> + { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ >> + { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ >> + { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ >> + { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ >> + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ >> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ >> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ >> }; >> >> -/* FIXME - After table is updated in Bspec */ >> -/* Voltage Swing Programming for VccIO 1.05V for eDP */ >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = { >> - /* Voltage mV db */ >> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ >> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ >> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ >> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ >> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ >> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = { >> + /* NT mV Trans mV db */ >> + { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ >> }; >> >> struct icl_mg_phy_ddi_buf_trans { >> @@ -870,43 +830,27 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) >> } >> } >> >> -static const struct icl_combo_phy_ddi_buf_trans * >> +static const struct cnl_ddi_buf_trans * >> icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port, >> int type, int *n_entries) >> { >> - u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK; >> >> if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { >> - switch (voltage) { >> - case VOLTAGE_INFO_0_85V: >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V); >> - return icl_combo_phy_ddi_translations_edp_0_85V; >> - case VOLTAGE_INFO_0_95V: >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V); >> - return icl_combo_phy_ddi_translations_edp_0_95V; >> - case VOLTAGE_INFO_1_05V: >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V); >> - return icl_combo_phy_ddi_translations_edp_1_05V; >> - default: >> - MISSING_CASE(voltage); >> - return NULL; >> - } >> - } else { >> - switch (voltage) { >> - case VOLTAGE_INFO_0_85V: >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V); >> - return icl_combo_phy_ddi_translations_dp_hdmi_0_85V; >> - case VOLTAGE_INFO_0_95V: >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V); >> - return icl_combo_phy_ddi_translations_dp_hdmi_0_95V; >> - case VOLTAGE_INFO_1_05V: >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V); >> - return icl_combo_phy_ddi_translations_dp_hdmi_1_05V; >> - default: >> - MISSING_CASE(voltage); >> - return NULL; >> - } >> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing); >> + return icl_combo_phy_ddi_translations_edp_lowswing; >> + } else if (type == INTEL_OUTPUT_EDP) { >> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); >> + return icl_combo_phy_ddi_translations_edp_hbr3; >> + } else if ((type == INTEL_OUTPUT_DP) || (type == INTEL_OUTPUT_DDI) || >> + (type == INTEL_OUTPUT_DP_MST)) { > I would move the hdmi case first to match how most other platforms do > it, and to eliminate this complicated DP check. Agreed. > >> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp); >> + return icl_combo_phy_ddi_translations_dp; >> + } else if (type == INTEL_OUTPUT_HDMI) { >> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); >> + return icl_combo_phy_ddi_translations_hdmi; >> } >> + >> + return NULL; >> } >> >> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) >> @@ -2463,7 +2407,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, >> static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, >> u32 level, enum port port, int type) >> { >> - const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL; >> + const struct cnl_ddi_buf_trans *ddi_translations = NULL; >> u32 n_entries, val; >> int ln; >> >> @@ -2477,34 +2421,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, >> level = n_entries - 1; >> } >> >> - /* Set PORT_TX_DW5 Rterm Sel to 110b. */ >> + /* Set PORT_TX_DW5 */ >> val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); >> - val &= ~RTERM_SELECT_MASK; >> + val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | >> + TAP2_DISABLE | TAP3_DISABLE); >> + val |= SCALING_MODE_SEL(0x2); >> val |= RTERM_SELECT(0x6); >> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); >> - >> - /* Program PORT_TX_DW5 */ >> - val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); >> - /* Set DisableTap2 and DisableTap3 if MIPI DSI >> - * Clear DisableTap2 and DisableTap3 for all other Ports >> - */ >> - if (type == INTEL_OUTPUT_DSI) { >> - val |= TAP2_DISABLE; >> - val |= TAP3_DISABLE; >> - } else { >> - val &= ~TAP2_DISABLE; >> - val &= ~TAP3_DISABLE; >> - } >> + val |= TAP3_DISABLE; >> I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); >> >> /* Program PORT_TX_DW2 */ >> val = I915_READ(ICL_PORT_TX_DW2_LN0(port)); >> val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | >> RCOMP_SCALAR_MASK); >> - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select); >> - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select); >> + val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); >> + val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); >> /* Program Rcomp scalar for every table entry */ >> - val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar); >> + val |= RCOMP_SCALAR(0x98); >> I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val); >> >> /* Program PORT_TX_DW4 */ >> @@ -2513,9 +2446,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, >> val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln)); >> val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | >> CURSOR_COEFF_MASK); >> - val |= ddi_translations[level].dw4_scaling; >> + val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); >> + val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); >> + val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); >> I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val); >> } >> + >> + /* Program PORT_TX_DW7 */ > The comment is redundant. It's consistent with the other comments in the function. The CNL function also has the exact same comment. Are you sure you want me to remove this comment? -Clint > >> + val = I915_READ(ICL_PORT_TX_DW7_LN0(port)); >> + val &= ~N_SCALAR_MASK; >> + val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); >> + I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val); >> } >> >> static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >> index 789f647bd..6c125ae 100644 >> --- a/drivers/gpu/drm/i915/intel_display.c >> +++ b/drivers/gpu/drm/i915/intel_display.c >> @@ -15435,9 +15435,6 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) >> >> /* notify opregion of the sanitized encoder state */ >> intel_opregion_notify_encoder(encoder, connector && has_active_crtc); >> - >> - if (INTEL_GEN(dev_priv) >= 11) >> - icl_sanitize_encoder_pll_mapping(encoder); >> } >> >> void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) >> -- >> 1.9.1
On Mon, Dec 03, 2018 at 11:34:16AM -0800, Clint Taylor wrote: > > > On 12/03/2018 04:19 AM, Ville Syrjälä wrote: > > On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.taylor@intel.com wrote: > >> From: Clint Taylor <clinton.a.taylor@intel.com> > >> > >> In August 2018 the BSPEC changed the ICL port programming sequence to > >> closely resemble earlier gen programming sequence. > >> > >> BSpec: 21257 > >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > >> Cc: Imre Deak <imre.deak@intel.com> > >> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > >> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> > >> --- > >> drivers/gpu/drm/i915/i915_reg.h | 4 + > >> drivers/gpu/drm/i915/intel_ddi.c | 223 +++++++++++++---------------------- > >> drivers/gpu/drm/i915/intel_display.c | 3 - > >> 3 files changed, 86 insertions(+), 144 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > >> index d3ef979..e632e99 100644 > >> --- a/drivers/gpu/drm/i915/i915_reg.h > >> +++ b/drivers/gpu/drm/i915/i915_reg.h > >> @@ -1866,6 +1866,10 @@ enum i915_power_well_id { > >> > >> #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7)) > >> #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7)) > >> +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port)) > >> +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port)) > >> +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port)) > >> +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port)) > >> #define N_SCALAR(x) ((x) << 24) > >> #define N_SCALAR_MASK (0x7F << 24) > >> > >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > >> index 61d7145..219464e9 100644 > >> --- a/drivers/gpu/drm/i915/intel_ddi.c > >> +++ b/drivers/gpu/drm/i915/intel_ddi.c > >> @@ -493,103 +493,63 @@ struct cnl_ddi_buf_trans { > >> { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ > >> }; > >> > >> -struct icl_combo_phy_ddi_buf_trans { > >> - u32 dw2_swing_select; > >> - u32 dw2_swing_scalar; > >> - u32 dw4_scaling; > >> -}; > >> - > >> -/* Voltage Swing Programming for VccIO 0.85V for DP */ > >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = { > >> - /* Voltage mV db */ > >> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ > >> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ > >> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ > >> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ > >> - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */ > >> - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */ > >> - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */ > >> - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */ > >> - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */ > >> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ > >> -}; > >> - > >> -/* FIXME - After table is updated in Bspec */ > >> -/* Voltage Swing Programming for VccIO 0.85V for eDP */ > >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = { > >> - /* Voltage mV db */ > >> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ > >> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ > >> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ > >> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ > >> +/* icl_combo_phy_ddi_translations */ > >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = { > >> + /* NT mV Trans mV db */ > >> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > >> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ > >> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ > >> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ > >> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ > >> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ > >> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ > >> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */ > >> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ > >> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ > >> }; > >> > >> -/* Voltage Swing Programming for VccIO 0.95V for DP */ > >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = { > >> - /* Voltage mV db */ > >> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ > >> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ > >> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ > >> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ > >> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */ > >> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */ > >> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */ > >> - { 0x5, 0x76, 0x0018 }, /* 800 0.0 */ > >> - { 0x5, 0x76, 0x3015 }, /* 800 3.5 */ > >> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ > >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = { > >> + /* NT mV Trans mV db */ > >> + { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > >> + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ > >> + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ > >> + { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ > >> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > >> + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ > >> + { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ > >> + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > >> + { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > >> + { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > >> }; > >> > >> -/* FIXME - After table is updated in Bspec */ > >> -/* Voltage Swing Programming for VccIO 0.95V for eDP */ > >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = { > >> - /* Voltage mV db */ > >> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ > >> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ > >> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ > >> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ > >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { > >> + /* NT mV Trans mV db */ > >> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > >> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ > >> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ > >> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ > >> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ > >> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ > >> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ > >> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ > >> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ > >> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ > >> }; > >> > >> -/* Voltage Swing Programming for VccIO 1.05V for DP */ > >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = { > >> - /* Voltage mV db */ > >> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ > >> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ > >> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ > >> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ > >> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */ > >> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */ > >> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */ > >> - { 0x5, 0x71, 0x0018 }, /* 800 0.0 */ > >> - { 0x5, 0x71, 0x3015 }, /* 800 3.5 */ > >> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ > >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { > >> + /* NT mV Trans mV db */ > >> + { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ > >> + { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ > >> + { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ > >> + { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ > >> + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ > >> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ > >> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ > >> }; > >> > >> -/* FIXME - After table is updated in Bspec */ > >> -/* Voltage Swing Programming for VccIO 1.05V for eDP */ > >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = { > >> - /* Voltage mV db */ > >> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ > >> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ > >> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ > >> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ > >> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ > >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = { > >> + /* NT mV Trans mV db */ > >> + { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ > >> }; > >> > >> struct icl_mg_phy_ddi_buf_trans { > >> @@ -870,43 +830,27 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) > >> } > >> } > >> > >> -static const struct icl_combo_phy_ddi_buf_trans * > >> +static const struct cnl_ddi_buf_trans * > >> icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port, > >> int type, int *n_entries) > >> { > >> - u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK; > >> > >> if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { > >> - switch (voltage) { > >> - case VOLTAGE_INFO_0_85V: > >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V); > >> - return icl_combo_phy_ddi_translations_edp_0_85V; > >> - case VOLTAGE_INFO_0_95V: > >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V); > >> - return icl_combo_phy_ddi_translations_edp_0_95V; > >> - case VOLTAGE_INFO_1_05V: > >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V); > >> - return icl_combo_phy_ddi_translations_edp_1_05V; > >> - default: > >> - MISSING_CASE(voltage); > >> - return NULL; > >> - } > >> - } else { > >> - switch (voltage) { > >> - case VOLTAGE_INFO_0_85V: > >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V); > >> - return icl_combo_phy_ddi_translations_dp_hdmi_0_85V; > >> - case VOLTAGE_INFO_0_95V: > >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V); > >> - return icl_combo_phy_ddi_translations_dp_hdmi_0_95V; > >> - case VOLTAGE_INFO_1_05V: > >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V); > >> - return icl_combo_phy_ddi_translations_dp_hdmi_1_05V; > >> - default: > >> - MISSING_CASE(voltage); > >> - return NULL; > >> - } > >> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing); > >> + return icl_combo_phy_ddi_translations_edp_lowswing; > >> + } else if (type == INTEL_OUTPUT_EDP) { > >> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); > >> + return icl_combo_phy_ddi_translations_edp_hbr3; > >> + } else if ((type == INTEL_OUTPUT_DP) || (type == INTEL_OUTPUT_DDI) || > >> + (type == INTEL_OUTPUT_DP_MST)) { > > I would move the hdmi case first to match how most other platforms do > > it, and to eliminate this complicated DP check. > Agreed. > > > >> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp); > >> + return icl_combo_phy_ddi_translations_dp; > >> + } else if (type == INTEL_OUTPUT_HDMI) { > >> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); > >> + return icl_combo_phy_ddi_translations_hdmi; > >> } > >> + > >> + return NULL; > >> } > >> > >> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) > >> @@ -2463,7 +2407,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, > >> static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > >> u32 level, enum port port, int type) > >> { > >> - const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL; > >> + const struct cnl_ddi_buf_trans *ddi_translations = NULL; > >> u32 n_entries, val; > >> int ln; > >> > >> @@ -2477,34 +2421,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > >> level = n_entries - 1; > >> } > >> > >> - /* Set PORT_TX_DW5 Rterm Sel to 110b. */ > >> + /* Set PORT_TX_DW5 */ > >> val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > >> - val &= ~RTERM_SELECT_MASK; > >> + val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | > >> + TAP2_DISABLE | TAP3_DISABLE); > >> + val |= SCALING_MODE_SEL(0x2); > >> val |= RTERM_SELECT(0x6); > >> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); > >> - > >> - /* Program PORT_TX_DW5 */ > >> - val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > >> - /* Set DisableTap2 and DisableTap3 if MIPI DSI > >> - * Clear DisableTap2 and DisableTap3 for all other Ports > >> - */ > >> - if (type == INTEL_OUTPUT_DSI) { > >> - val |= TAP2_DISABLE; > >> - val |= TAP3_DISABLE; > >> - } else { > >> - val &= ~TAP2_DISABLE; > >> - val &= ~TAP3_DISABLE; > >> - } > >> + val |= TAP3_DISABLE; > >> I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); > >> > >> /* Program PORT_TX_DW2 */ > >> val = I915_READ(ICL_PORT_TX_DW2_LN0(port)); > >> val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | > >> RCOMP_SCALAR_MASK); > >> - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select); > >> - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select); > >> + val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); > >> + val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); > >> /* Program Rcomp scalar for every table entry */ > >> - val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar); > >> + val |= RCOMP_SCALAR(0x98); > >> I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val); > >> > >> /* Program PORT_TX_DW4 */ > >> @@ -2513,9 +2446,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > >> val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln)); > >> val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | > >> CURSOR_COEFF_MASK); > >> - val |= ddi_translations[level].dw4_scaling; > >> + val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); > >> + val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); > >> + val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); > >> I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val); > >> } > >> + > >> + /* Program PORT_TX_DW7 */ > > The comment is redundant. > It's consistent with the other comments in the function. The CNL > function also has the exact same comment. Are you sure you want me to > remove this comment? Meh. I guess keep it it it's consistent with the rest. Or send a patch to nuke all the redundant comments.
On Tue, Dec 18, 2018 at 12:35:30AM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev5) > URL : https://patchwork.freedesktop.org/series/53340/ > State : success Pushed to -dinq, thanks for the patch and review. > > == Summary == > > CI Bug Log - changes from CI_DRM_5325_full -> Patchwork_11110_full > ==================================================== > > Summary > ------- > > **WARNING** > > Minor unknown changes coming with Patchwork_11110_full need to be verified > manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_11110_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_11110_full: > > ### IGT changes ### > > #### Warnings #### > > * igt@pm_rc6_residency@rc6-accuracy: > - shard-snb: SKIP -> PASS > > > Known issues > ------------ > > Here are the changes found in Patchwork_11110_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_exec_schedule@pi-ringfull-blt: > - shard-skl: NOTRUN -> FAIL [fdo#103158] +1 > > * igt@gem_exec_schedule@pi-ringfull-vebox: > - shard-iclb: NOTRUN -> FAIL [fdo#103158] > > * igt@gem_softpin@noreloc-s3: > - shard-iclb: PASS -> INCOMPLETE [fdo#107713] > > * igt@gem_userptr_blits@readonly-unsync: > - shard-skl: NOTRUN -> TIMEOUT [fdo#108887] > > * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: > - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] > > * igt@kms_ccs@pipe-a-crc-sprite-planes-basic: > - shard-glk: PASS -> FAIL [fdo#108145] > > * igt@kms_cursor_crc@cursor-128x42-onscreen: > - shard-iclb: NOTRUN -> FAIL [fdo#103232] > > * igt@kms_cursor_crc@cursor-256x256-sliding: > - shard-glk: PASS -> FAIL [fdo#103232] +1 > > * igt@kms_cursor_crc@cursor-64x21-random: > - shard-apl: PASS -> FAIL [fdo#103232] > > * igt@kms_cursor_crc@cursor-64x64-offscreen: > - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +1 > > * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-xtiled: > - shard-iclb: PASS -> WARN [fdo#108336] > > * igt@kms_flip@flip-vs-expired-vblank-interruptible: > - shard-kbl: PASS -> FAIL [fdo#102887] / [fdo#105363] > > * igt@kms_flip@flip-vs-rmfb-interruptible: > - shard-apl: PASS -> INCOMPLETE [fdo#103927] > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: > - shard-iclb: NOTRUN -> FAIL [fdo#103167] > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: > - shard-apl: PASS -> FAIL [fdo#103167] +2 > > * igt@kms_frontbuffer_tracking@fbcpsr-suspend: > - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#106978] / [fdo#107773] > > * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen: > - shard-iclb: PASS -> FAIL [fdo#103167] +2 > > * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: > - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] > > * igt@kms_plane@pixel-format-pipe-c-planes: > - shard-apl: PASS -> FAIL [fdo#103166] > - shard-glk: PASS -> FAIL [fdo#103166] +1 > > * igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb: > - shard-iclb: PASS -> DMESG-FAIL [fdo#107724] > > * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb: > - shard-apl: PASS -> FAIL [fdo#108145] > > * igt@kms_psr@primary_render: > - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +3 > > * igt@kms_setmode@basic: > - shard-kbl: PASS -> FAIL [fdo#99912] > > * igt@kms_sysfs_edid_timing: > - shard-skl: NOTRUN -> FAIL [fdo#100047] > > * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend: > - shard-kbl: PASS -> INCOMPLETE [fdo#103665] > > * {igt@runner@aborted}: > - shard-iclb: NOTRUN -> FAIL [fdo#108866] > > > #### Possible fixes #### > > * igt@gem_eio@in-flight-contexts-immediate: > - shard-glk: FAIL [fdo#107799] -> PASS > > * igt@gem_workarounds@suspend-resume-fd: > - shard-iclb: INCOMPLETE [fdo#107713] -> PASS +1 > > * igt@kms_cursor_crc@cursor-256x256-onscreen: > - shard-skl: FAIL [fdo#103232] -> PASS > > * igt@kms_cursor_crc@cursor-256x256-random: > - shard-glk: FAIL [fdo#103232] -> PASS +2 > - shard-apl: FAIL [fdo#103232] -> PASS +3 > > * igt@kms_flip@flip-vs-expired-vblank: > - shard-skl: FAIL [fdo#105363] -> PASS > > * igt@kms_flip@modeset-vs-vblank-race-interruptible: > - shard-apl: FAIL [fdo#103060] -> PASS > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: > - shard-apl: FAIL [fdo#103167] -> PASS +2 > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: > - shard-glk: FAIL [fdo#103167] -> PASS +2 > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: > - shard-iclb: FAIL [fdo#103167] -> PASS +6 > > * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: > - shard-skl: FAIL [fdo#103191] / [fdo#107362] -> PASS > > * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: > - shard-apl: FAIL [fdo#108948] -> PASS > > * igt@kms_plane@plane-position-covered-pipe-c-planes: > - shard-glk: FAIL [fdo#103166] -> PASS +1 > > * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-skl: FAIL [fdo#107815] / [fdo#108145] -> PASS > > * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: > - shard-skl: FAIL [fdo#107815] -> PASS > > * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: > - shard-apl: FAIL [fdo#103166] -> PASS +2 > - shard-iclb: FAIL [fdo#103166] -> PASS > > * igt@pm_rpm@debugfs-read: > - shard-iclb: DMESG-WARN [fdo#108654] -> PASS > > * igt@pm_rpm@dpms-lpsp: > - shard-iclb: DMESG-WARN [fdo#107724] -> PASS > > * igt@pm_rpm@gem-execbuf-stress-extra-wait: > - shard-skl: INCOMPLETE [fdo#107803] / [fdo#107807] -> PASS > > * igt@pm_rpm@modeset-non-lpsp-stress-no-wait: > - shard-iclb: INCOMPLETE [fdo#108840] -> SKIP > > > #### Warnings #### > > * igt@i915_selftest@live_contexts: > - shard-iclb: DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108315] > > * igt@kms_ccs@pipe-a-crc-primary-basic: > - shard-iclb: FAIL [fdo#107725] -> DMESG-WARN [fdo#107724] / [fdo#108336] > > * igt@kms_rotation_crc@multiplane-rotation-cropping-top: > - shard-kbl: DMESG-WARN [fdo#105604] -> DMESG-FAIL [fdo#108950] > - shard-glk: DMESG-WARN [fdo#105763] / [fdo#106538] -> DMESG-FAIL [fdo#105763] / [fdo#106538] > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047 > [fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887 > [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060 > [fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158 > [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 > [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 > [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 > [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 > [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 > [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 > [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 > [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363 > [fdo#105604]: https://bugs.freedesktop.org/show_bug.cgi?id=105604 > [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763 > [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538 > [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885 > [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978 > [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 > [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 > [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 > [fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725 > [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773 > [fdo#107799]: https://bugs.freedesktop.org/show_bug.cgi?id=107799 > [fdo#107803]: https://bugs.freedesktop.org/show_bug.cgi?id=107803 > [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 > [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815 > [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956 > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#108315]: https://bugs.freedesktop.org/show_bug.cgi?id=108315 > [fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336 > [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 > [fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654 > [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840 > [fdo#108866]: https://bugs.freedesktop.org/show_bug.cgi?id=108866 > [fdo#108887]: https://bugs.freedesktop.org/show_bug.cgi?id=108887 > [fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948 > [fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950 > [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 > > > Participating hosts (7 -> 7) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_5325 -> Patchwork_11110 > > CI_DRM_5325: d1085cddae920b9a0c326e3cc3e342cfee14aed2 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_4749: 270da20849db4d170db09673c6b67712c90ec9fe @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_11110: 2a15cd7c794ae90e2d6de66015665e9a985a2467 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11110/ > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d3ef979..e632e99 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1866,6 +1866,10 @@ enum i915_power_well_id { #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7)) #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7)) +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port)) +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port)) +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port)) +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port)) #define N_SCALAR(x) ((x) << 24) #define N_SCALAR_MASK (0x7F << 24) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 61d7145..219464e9 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -493,103 +493,63 @@ struct cnl_ddi_buf_trans { { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ }; -struct icl_combo_phy_ddi_buf_trans { - u32 dw2_swing_select; - u32 dw2_swing_scalar; - u32 dw4_scaling; -}; - -/* Voltage Swing Programming for VccIO 0.85V for DP */ -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = { - /* Voltage mV db */ - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */ - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */ - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */ - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */ - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */ - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ -}; - -/* FIXME - After table is updated in Bspec */ -/* Voltage Swing Programming for VccIO 0.85V for eDP */ -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = { - /* Voltage mV db */ - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ +/* icl_combo_phy_ddi_translations */ +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = { + /* NT mV Trans mV db */ + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */ + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ }; -/* Voltage Swing Programming for VccIO 0.95V for DP */ -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = { - /* Voltage mV db */ - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */ - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */ - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */ - { 0x5, 0x76, 0x0018 }, /* 800 0.0 */ - { 0x5, 0x76, 0x3015 }, /* 800 3.5 */ - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = { + /* NT mV Trans mV db */ + { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ + { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ + { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ + { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ + { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ }; -/* FIXME - After table is updated in Bspec */ -/* Voltage Swing Programming for VccIO 0.95V for eDP */ -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = { - /* Voltage mV db */ - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { + /* NT mV Trans mV db */ + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ }; -/* Voltage Swing Programming for VccIO 1.05V for DP */ -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = { - /* Voltage mV db */ - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */ - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */ - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */ - { 0x2, 0x98, 0x900F }, /* 400 9.5 */ - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */ - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */ - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */ - { 0x5, 0x71, 0x0018 }, /* 800 0.0 */ - { 0x5, 0x71, 0x3015 }, /* 800 3.5 */ - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */ +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { + /* NT mV Trans mV db */ + { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ + { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ + { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ + { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ }; -/* FIXME - After table is updated in Bspec */ -/* Voltage Swing Programming for VccIO 1.05V for eDP */ -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = { - /* Voltage mV db */ - { 0x0, 0x00, 0x00 }, /* 200 0.0 */ - { 0x0, 0x00, 0x00 }, /* 200 1.5 */ - { 0x0, 0x00, 0x00 }, /* 200 4.0 */ - { 0x0, 0x00, 0x00 }, /* 200 6.0 */ - { 0x0, 0x00, 0x00 }, /* 250 0.0 */ - { 0x0, 0x00, 0x00 }, /* 250 1.5 */ - { 0x0, 0x00, 0x00 }, /* 250 4.0 */ - { 0x0, 0x00, 0x00 }, /* 300 0.0 */ - { 0x0, 0x00, 0x00 }, /* 300 1.5 */ - { 0x0, 0x00, 0x00 }, /* 350 0.0 */ +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = { + /* NT mV Trans mV db */ + { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ }; struct icl_mg_phy_ddi_buf_trans { @@ -870,43 +830,27 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) } } -static const struct icl_combo_phy_ddi_buf_trans * +static const struct cnl_ddi_buf_trans * icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port, int type, int *n_entries) { - u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK; if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { - switch (voltage) { - case VOLTAGE_INFO_0_85V: - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V); - return icl_combo_phy_ddi_translations_edp_0_85V; - case VOLTAGE_INFO_0_95V: - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V); - return icl_combo_phy_ddi_translations_edp_0_95V; - case VOLTAGE_INFO_1_05V: - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V); - return icl_combo_phy_ddi_translations_edp_1_05V; - default: - MISSING_CASE(voltage); - return NULL; - } - } else { - switch (voltage) { - case VOLTAGE_INFO_0_85V: - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V); - return icl_combo_phy_ddi_translations_dp_hdmi_0_85V; - case VOLTAGE_INFO_0_95V: - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V); - return icl_combo_phy_ddi_translations_dp_hdmi_0_95V; - case VOLTAGE_INFO_1_05V: - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V); - return icl_combo_phy_ddi_translations_dp_hdmi_1_05V; - default: - MISSING_CASE(voltage); - return NULL; - } + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing); + return icl_combo_phy_ddi_translations_edp_lowswing; + } else if (type == INTEL_OUTPUT_EDP) { + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); + return icl_combo_phy_ddi_translations_edp_hbr3; + } else if ((type == INTEL_OUTPUT_DP) || (type == INTEL_OUTPUT_DDI) || + (type == INTEL_OUTPUT_DP_MST)) { + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp); + return icl_combo_phy_ddi_translations_dp; + } else if (type == INTEL_OUTPUT_HDMI) { + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); + return icl_combo_phy_ddi_translations_hdmi; } + + return NULL; } static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) @@ -2463,7 +2407,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, u32 level, enum port port, int type) { - const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL; + const struct cnl_ddi_buf_trans *ddi_translations = NULL; u32 n_entries, val; int ln; @@ -2477,34 +2421,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, level = n_entries - 1; } - /* Set PORT_TX_DW5 Rterm Sel to 110b. */ + /* Set PORT_TX_DW5 */ val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); - val &= ~RTERM_SELECT_MASK; + val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | + TAP2_DISABLE | TAP3_DISABLE); + val |= SCALING_MODE_SEL(0x2); val |= RTERM_SELECT(0x6); - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); - - /* Program PORT_TX_DW5 */ - val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); - /* Set DisableTap2 and DisableTap3 if MIPI DSI - * Clear DisableTap2 and DisableTap3 for all other Ports - */ - if (type == INTEL_OUTPUT_DSI) { - val |= TAP2_DISABLE; - val |= TAP3_DISABLE; - } else { - val &= ~TAP2_DISABLE; - val &= ~TAP3_DISABLE; - } + val |= TAP3_DISABLE; I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); /* Program PORT_TX_DW2 */ val = I915_READ(ICL_PORT_TX_DW2_LN0(port)); val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | RCOMP_SCALAR_MASK); - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select); - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select); + val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); + val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); /* Program Rcomp scalar for every table entry */ - val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar); + val |= RCOMP_SCALAR(0x98); I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val); /* Program PORT_TX_DW4 */ @@ -2513,9 +2446,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln)); val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK); - val |= ddi_translations[level].dw4_scaling; + val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); + val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); + val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val); } + + /* Program PORT_TX_DW7 */ + val = I915_READ(ICL_PORT_TX_DW7_LN0(port)); + val &= ~N_SCALAR_MASK; + val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); + I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val); } static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 789f647bd..6c125ae 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -15435,9 +15435,6 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) /* notify opregion of the sanitized encoder state */ intel_opregion_notify_encoder(encoder, connector && has_active_crtc); - - if (INTEL_GEN(dev_priv) >= 11) - icl_sanitize_encoder_pll_mapping(encoder); } void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)