diff mbox series

[CI,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define

Message ID 20181130213304.17329-1-lucas.demarchi@intel.com (mailing list archive)
State New, archived
Headers show
Series [CI,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define | expand

Commit Message

Lucas De Marchi Nov. 30, 2018, 9:33 p.m. UTC 
From: Tomasz Lis <tomasz.lis@intel.com>

The MOCS tables are going to be very similar across platforms.

To reduce the amount of copied code, this patch rips the common part and
puts it into a definition valid for all gen9 platforms.

v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
    to MOCS_ENTRIES. (Joonas)

Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> (v1)
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_mocs.c | 86 +++++++++++++------------------
 1 file changed, 36 insertions(+), 50 deletions(-)

Comments

Chris Wilson Nov. 30, 2018, 9:59 p.m. UTC | #1 
Quoting Lucas De Marchi (2018-11-30 21:33:03)
> From: Tomasz Lis <tomasz.lis@intel.com>
> 
> The MOCS tables are going to be very similar across platforms.
> 
> To reduce the amount of copied code, this patch rips the common part and
> puts it into a definition valid for all gen9 platforms.
> 
> v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
>     to MOCS_ENTRIES. (Joonas)
> 
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> (v1)

Lucas, this needs your s-o-b if you are sending it for inclusion (to
state that you do have the legal authority to do so).
-Chris
Chris Wilson Nov. 30, 2018, 11:35 p.m. UTC | #2 
Quoting Lucas De Marchi (2018-11-30 23:19:18)
> On Fri, Nov 30, 2018 at 09:59:53PM +0000, Chris Wilson wrote:
> > Quoting Lucas De Marchi (2018-11-30 21:33:03)
> > > From: Tomasz Lis <tomasz.lis@intel.com>
> > > 
> > > The MOCS tables are going to be very similar across platforms.
> > > 
> > > To reduce the amount of copied code, this patch rips the common part and
> > > puts it into a definition valid for all gen9 platforms.
> > > 
> > > v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
> > >     to MOCS_ENTRIES. (Joonas)
> > > 
> > > Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> > > Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> (v1)
> > 
> > Lucas, this needs your s-o-b if you are sending it for inclusion (to
> > state that you do have the legal authority to do so).
> 
> Did I misunderstand the meaning of the CI tag? These are exactly the
> same commits as https://patchwork.freedesktop.org/series/51258/
> I'm only sending again to get them to run properly on CI since patchwork
> got confused with the in-reply-to used there.
> 
> And I'm not going to apply these myself, so adding the s-o-b didn't seem
> appropriate.

If you ask someone else to apply this series as is, it has passed
through your hands and you need to affirm that you do have authority to
be supplying these patches.

I may have misunderstood your intent (if the commits remained the same
as before, you could have just requeued the earlier series for testing)
as I thought your intent here was to get CI results before applying
these patches (be that yourself or by proxy).
-Chris
Chris Wilson Nov. 30, 2018, 11:37 p.m. UTC | #3 
Quoting Chris Wilson (2018-11-30 23:35:25)
> I may have misunderstood your intent (if the commits remained the same
> as before, you could have just requeued the earlier series for testing)
> as I thought your intent here was to get CI results before applying
> these patches (be that yourself or by proxy).

Or perhaps even more appropriate would have been to use intel-gfx-trybot@
if this was just for private retesting.
-Chris
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 77e9871a8c9a..8d08a7b7d534 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -96,71 +96,57 @@  struct drm_i915_mocs_table {
  *       may only be updated incrementally by adding entries at the
  *       end.
  */
-static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
-	[I915_MOCS_UNCACHED] = {
-	  /* 0x00000009 */
-	  .control_value = LE_CACHEABILITY(LE_UC) |
-			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-			   LE_PFM(0) | LE_SCF(0),
-
-	  /* 0x0010 */
-	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
-	},
-	[I915_MOCS_PTE] = {
-	  /* 0x00000038 */
-	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
-			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-			   LE_PFM(0) | LE_SCF(0),
-	  /* 0x0030 */
-	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+
+#define MOCS_CONTROL_VALUE(lecc, tc, lrum, daom, ersc, scc, pfm, scf) \
+	(LE_CACHEABILITY(lecc) | LE_TGT_CACHE(tc) | \
+	LE_LRUM(lrum) | LE_AOM(daom) | LE_RSC(ersc) | LE_SCC(scc) | \
+	LE_PFM(pfm) | LE_SCF(scf))
+
+#define MOCS_L3CC_VALUE(esc, scc, l3cc) \
+	(L3_ESC(esc) | L3_SCC(scc) | L3_CACHEABILITY(l3cc))
+
+#define GEN9_MOCS_ENTRIES \
+	[I915_MOCS_UNCACHED] = { \
+	  /* 0x00000009 */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC_ELLC, \
+					      0, 0, 0, 0, 0, 0), \
+	  /* 0x0010 */ \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+	}, \
+	[I915_MOCS_PTE] = { \
+	  /* 0x00000038 */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_PAGETABLE, LE_TC_LLC_ELLC, \
+					      3, 0, 0, 0, 0, 0), \
+	  /* 0x0030 */ \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
 	},
+
+static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
+	GEN9_MOCS_ENTRIES
 	[I915_MOCS_CACHED] = {
 	  /* 0x0000003b */
-	  .control_value = LE_CACHEABILITY(LE_WB) |
-			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-			   LE_PFM(0) | LE_SCF(0),
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC_ELLC,
+					      3, 0, 0, 0, 0, 0),
 	  /* 0x0030 */
-	  .l3cc_value =   L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB),
 	},
 };
 
 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
-	[I915_MOCS_UNCACHED] = {
-	  /* 0x00000009 */
-	  .control_value = LE_CACHEABILITY(LE_UC) |
-			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-			   LE_PFM(0) | LE_SCF(0),
-
-	  /* 0x0010 */
-	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
-	},
-	[I915_MOCS_PTE] = {
-	  /* 0x00000038 */
-	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
-			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-			   LE_PFM(0) | LE_SCF(0),
-
-	  /* 0x0030 */
-	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
-	},
+	GEN9_MOCS_ENTRIES
 	[I915_MOCS_CACHED] = {
 	  /* 0x00000039 */
-	  .control_value = LE_CACHEABILITY(LE_UC) |
-			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-			   LE_PFM(0) | LE_SCF(0),
-
+	  .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC_ELLC,
+					      3, 0, 0, 0, 0, 0),
 	  /* 0x0030 */
-	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB),
 	},
 };
 
+#undef MOCS_CONTROL_VALUE
+#undef MOCS_L3CC_VALUE
+
 /**
  * get_mocs_settings()
  * @dev_priv:	i915 device.