| Message ID | 1543347887-21101-5-git-send-email-will.deacon@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Rewrite of percpu atomics and introduction of LSE | expand |
On Tue, 27 Nov 2018 at 20:44, Will Deacon <will.deacon@arm.com> wrote: > > The "L" AArch64 machine constraint, which we use for the "old" value in > an LL/SC cmpxchg(), generates an immediate that is suitable for a 64-bit > logical instruction. However, for cmpxchg() operations on types smaller > than 64 bits, this constraint can result in an invalid instruction which > is correctly rejected by GAS, such as EOR W1, W1, #0xffffffff. > > Whilst we could special-case the constraint based on the cmpxchg size, > it's far easier to change the constraint to "K" and put up with using > a register for large 64-bit immediates. For out-of-line LL/SC atomics, > this is all moot anyway. > > Reported-by: Robin Murphy <robin.murphy@arm.com> > Signed-off-by: Will Deacon <will.deacon@arm.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > --- > arch/arm64/include/asm/atomic_ll_sc.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/atomic_ll_sc.h b/arch/arm64/include/asm/atomic_ll_sc.h > index b53f70dd6e10..af7b99005453 100644 > --- a/arch/arm64/include/asm/atomic_ll_sc.h > +++ b/arch/arm64/include/asm/atomic_ll_sc.h > @@ -276,7 +276,7 @@ __LL_SC_PREFIX(__cmpxchg_case_##name##sz(volatile void *ptr, \ > "2:" \ > : [tmp] "=&r" (tmp), [oldval] "=&r" (oldval), \ > [v] "+Q" (*(u##sz *)ptr) \ > - : [old] "Lr" (old), [new] "r" (new) \ > + : [old] "Kr" (old), [new] "r" (new) \ > : cl); \ > \ > return oldval; \ > -- > 2.1.4 >
diff --git a/arch/arm64/include/asm/atomic_ll_sc.h b/arch/arm64/include/asm/atomic_ll_sc.h index b53f70dd6e10..af7b99005453 100644 --- a/arch/arm64/include/asm/atomic_ll_sc.h +++ b/arch/arm64/include/asm/atomic_ll_sc.h @@ -276,7 +276,7 @@ __LL_SC_PREFIX(__cmpxchg_case_##name##sz(volatile void *ptr, \ "2:" \ : [tmp] "=&r" (tmp), [oldval] "=&r" (oldval), \ [v] "+Q" (*(u##sz *)ptr) \ - : [old] "Lr" (old), [new] "r" (new) \ + : [old] "Kr" (old), [new] "r" (new) \ : cl); \ \ return oldval; \
The "L" AArch64 machine constraint, which we use for the "old" value in an LL/SC cmpxchg(), generates an immediate that is suitable for a 64-bit logical instruction. However, for cmpxchg() operations on types smaller than 64 bits, this constraint can result in an invalid instruction which is correctly rejected by GAS, such as EOR W1, W1, #0xffffffff. Whilst we could special-case the constraint based on the cmpxchg size, it's far easier to change the constraint to "K" and put up with using a register for large 64-bit immediates. For out-of-line LL/SC atomics, this is all moot anyway. Reported-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> --- arch/arm64/include/asm/atomic_ll_sc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)