| Message ID | 20181205221126.16220-1-paul.burton@mips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | atomic.h: Set ATOMIC_REG_SIZE=8 for MIPS n32 | expand |
On 12/5/18 4:11 PM, Paul Burton wrote: > ATOMIC_REG_SIZE is currently defined as the default sizeof(void *) for > all MIPS host builds, including those using the n32 ABI. n32 is the > MIPS64 ILP32 ABI and as such tcg/mips/tcg-target.h defines > TCG_TARGET_REG_BITS as 64 for n32 builds. If we attempt to build QEMU > for an n32 host with support for a 64b target architecture then > TCG_OVERSIZED_GUEST is 0 and accel/tcg/cputlb.c attempts to use atomic_* > functions. This fails because ATOMIC_REG_SIZE is 4, causing the calls to > QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE) in the various > atomic_* functions to generate errors. > > Fix this by defining ATOMIC_REG_SIZE as 8 for all MIPS64 builds, which > will cover both n32 (ILP32) & n64 (LP64) ABIs in much the same was as we > already do for x86_64/x32. > > Signed-off-by: Paul Burton <paul.burton@mips.com> > --- > include/qemu/atomic.h | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 12/5/18 11:11 PM, Paul Burton wrote: > ATOMIC_REG_SIZE is currently defined as the default sizeof(void *) for > all MIPS host builds, including those using the n32 ABI. n32 is the > MIPS64 ILP32 ABI and as such tcg/mips/tcg-target.h defines > TCG_TARGET_REG_BITS as 64 for n32 builds. If we attempt to build QEMU > for an n32 host with support for a 64b target architecture then > TCG_OVERSIZED_GUEST is 0 and accel/tcg/cputlb.c attempts to use atomic_* > functions. This fails because ATOMIC_REG_SIZE is 4, causing the calls to > QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE) in the various > atomic_* functions to generate errors. > > Fix this by defining ATOMIC_REG_SIZE as 8 for all MIPS64 builds, which > will cover both n32 (ILP32) & n64 (LP64) ABIs in much the same was as we > already do for x86_64/x32. > > Signed-off-by: Paul Burton <paul.burton@mips.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > --- > include/qemu/atomic.h | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h > index f6993a8fb1..a6ac188188 100644 > --- a/include/qemu/atomic.h > +++ b/include/qemu/atomic.h > @@ -99,9 +99,10 @@ > * those few cases by hand. > * > * Note that x32 is fully detected with __x86_64__ + _ILP32, and that for > - * Sparc we always force the use of sparcv9 in configure. > + * Sparc we always force the use of sparcv9 in configure. MIPS n32 (ILP32) & > + * n64 (LP64) ABIs are both detected using __mips64. > */ > -#if defined(__x86_64__) || defined(__sparc__) > +#if defined(__x86_64__) || defined(__sparc__) || defined(__mips64) > # define ATOMIC_REG_SIZE 8 > #else > # define ATOMIC_REG_SIZE sizeof(void *) >
> On 12/5/18 11:11 PM, Paul Burton wrote: > ATOMIC_REG_SIZE is currently defined as the default sizeof(void *) for > all MIPS host builds, including those using the n32 ABI. n32 is the > MIPS64 ILP32 ABI and as such tcg/mips/tcg-target.h defines > TCG_TARGET_REG_BITS as 64 for n32 builds. If we attempt to build QEMU > for an n32 host with support for a 64b target architecture then > TCG_OVERSIZED_GUEST is 0 and accel/tcg/cputlb.c attempts to use atomic_* > functions. This fails because ATOMIC_REG_SIZE is 4, causing the calls to > QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE) in the various > atomic_* functions to generate errors. > > Fix this by defining ATOMIC_REG_SIZE as 8 for all MIPS64 builds, which > will cover both n32 (ILP32) & n64 (LP64) ABIs in much the same was as we > already do for x86_64/x32. > > Signed-off-by: Paul Burton <paul.burton@mips.com> I am going to include this patch in next mips pull request scheduled for today or tomorrow. Aleksandar
diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index f6993a8fb1..a6ac188188 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -99,9 +99,10 @@ * those few cases by hand. * * Note that x32 is fully detected with __x86_64__ + _ILP32, and that for - * Sparc we always force the use of sparcv9 in configure. + * Sparc we always force the use of sparcv9 in configure. MIPS n32 (ILP32) & + * n64 (LP64) ABIs are both detected using __mips64. */ -#if defined(__x86_64__) || defined(__sparc__) +#if defined(__x86_64__) || defined(__sparc__) || defined(__mips64) # define ATOMIC_REG_SIZE 8 #else # define ATOMIC_REG_SIZE sizeof(void *)
ATOMIC_REG_SIZE is currently defined as the default sizeof(void *) for all MIPS host builds, including those using the n32 ABI. n32 is the MIPS64 ILP32 ABI and as such tcg/mips/tcg-target.h defines TCG_TARGET_REG_BITS as 64 for n32 builds. If we attempt to build QEMU for an n32 host with support for a 64b target architecture then TCG_OVERSIZED_GUEST is 0 and accel/tcg/cputlb.c attempts to use atomic_* functions. This fails because ATOMIC_REG_SIZE is 4, causing the calls to QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE) in the various atomic_* functions to generate errors. Fix this by defining ATOMIC_REG_SIZE as 8 for all MIPS64 builds, which will cover both n32 (ILP32) & n64 (LP64) ABIs in much the same was as we already do for x86_64/x32. Signed-off-by: Paul Burton <paul.burton@mips.com> --- include/qemu/atomic.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)