diff mbox series

clk: sunxi-ng: a64: Allow parent change for VE clock

Message ID 20181208180222.12608-1-jernej.skrabec@siol.net (mailing list archive)
State New, archived
Headers show
Series clk: sunxi-ng: a64: Allow parent change for VE clock | expand

Commit Message

Jernej Škrabec Dec. 8, 2018, 6:02 p.m. UTC 
Cedrus driver wants to set VE clock higher than it's possible without
changing parent rate.

Allow changing parent rate for VE clock, so clock rate can be set
freely.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Maxime Ripard Dec. 10, 2018, 12:40 p.m. UTC | #1 
On Sat, Dec 08, 2018 at 07:02:22PM +0100, Jernej Skrabec wrote:
> Cedrus driver wants to set VE clock higher than it's possible without
> changing parent rate.
> 
> Allow changing parent rate for VE clock, so clock rate can be set
> freely.
> 
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

Stephen, Mike, could you apply that patch directly?

Thanks!
Maxime
Stephen Boyd Dec. 10, 2018, 7:19 p.m. UTC | #2 
Quoting Maxime Ripard (2018-12-10 04:40:49)
> On Sat, Dec 08, 2018 at 07:02:22PM +0100, Jernej Skrabec wrote:
> > Cedrus driver wants to set VE clock higher than it's possible without
> > changing parent rate.
> > 
> > Allow changing parent rate for VE clock, so clock rate can be set
> > freely.
> > 
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> 
> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
> 
> Stephen, Mike, could you apply that patch directly?
> 

Sure. Applied to clk-allwinner and merged up.
diff mbox series

Patch

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 5f80eb018014..1e2cd37cf0b8 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -554,7 +554,7 @@  static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
 				 0x134, 0, 5, 8, 3, BIT(15), 0);
 
 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
-			     0x13c, 16, 3, BIT(31), 0);
+			     0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
 
 static SUNXI_CCU_GATE(ac_dig_clk,	"ac-dig",	"pll-audio",
 		      0x140, BIT(31), CLK_SET_RATE_PARENT);