| Message ID | 20181213093438.29621-19-josephl@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Tegra210 DFLL support | expand |
On 13/12/2018 09:34, Joseph Lo wrote: > Enable DFLL clock for Jetson TX1 platform. > > Signed-off-by: Joseph Lo <josephl@nvidia.com> > --- > *V2: > - remove non exist DT bindings > - update the PWM DT bindings accordingly > --- > .../boot/dts/nvidia/tegra210-p2371-2180.dts | 21 +++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts > index 37e3c46e753f..99c016bfc601 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts > +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts > @@ -78,4 +78,25 @@ > }; > }; > }; > + > + clock@70110000 { > + status = "okay"; > + > + nvidia,cf = <6>; > + nvidia,ci = <0>; > + nvidia,cg = <2>; > + nvidia,droop-ctrl = <0x00000f00>; > + nvidia,force-mode = <1>; > + nvidia,sample-rate = <25000>; > + > + nvidia,pwm-min-microvolts = <708000>; > + nvidia,pwm-period = <2500>; /* 2.5us */ > + nvidia,pwm-to-pmic; > + nvidia,pwm-tristate-microvolts = <1000000>; > + nvidia,pwm-voltage-step-microvolts = <19200>; > + > + pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; > + pinctrl-0 = <&dvfs_pwm_active_state>; > + pinctrl-1 = <&dvfs_pwm_inactive_state>; > + }; > }; Acked-by: Jon Hunter <jonathanh@nvidia.com> Cheers Jon
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 37e3c46e753f..99c016bfc601 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -78,4 +78,25 @@ }; }; }; + + clock@70110000 { + status = "okay"; + + nvidia,cf = <6>; + nvidia,ci = <0>; + nvidia,cg = <2>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,sample-rate = <25000>; + + nvidia,pwm-min-microvolts = <708000>; + nvidia,pwm-period = <2500>; /* 2.5us */ + nvidia,pwm-to-pmic; + nvidia,pwm-tristate-microvolts = <1000000>; + nvidia,pwm-voltage-step-microvolts = <19200>; + + pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; + pinctrl-0 = <&dvfs_pwm_active_state>; + pinctrl-1 = <&dvfs_pwm_inactive_state>; + }; };
Enable DFLL clock for Jetson TX1 platform. Signed-off-by: Joseph Lo <josephl@nvidia.com> --- *V2: - remove non exist DT bindings - update the PWM DT bindings accordingly --- .../boot/dts/nvidia/tegra210-p2371-2180.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+)