[v3,1/2] ARM: dts: r7s9210: Initial SoC device tree

Message ID	20181217144324.99422-2-chris.brandt@renesas.com (mailing list archive)
State	Superseded
Delegated to:	Simon Horman
Headers	show Return-Path: <linux-renesas-soc-owner@kernel.org> From: Chris Brandt <chris.brandt@renesas.com> To: Simon Horman <horms@verge.net.au>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Brandt <chris.brandt@renesas.com> Subject: [PATCH v3 1/2] ARM: dts: r7s9210: Initial SoC device tree Date: Mon, 17 Dec 2018 09:43:23 -0500 Message-Id: <20181217144324.99422-2-chris.brandt@renesas.com> In-Reply-To: <20181217144324.99422-1-chris.brandt@renesas.com> References: <20181217144324.99422-1-chris.brandt@renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk
Series	Add Initial Device Tree for RZ/A2 \| expand [v3,0/2] Add Initial Device Tree for RZ/A2 [v3,1/2] ARM: dts: r7s9210: Initial SoC device tree [v3,2/2] ARM: dts: r7s9210-rza2mevb: Add support for RZ/A2M EVB

Chris Brandt Dec. 17, 2018, 2:43 p.m. UTC

Basic support for the RZ/A2 (R7S9210) SoC.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
v2:
 * Fixed cpg node name to match reg address
 * Removed the clocks subnode
 * SCIF register range 18 to 0x18
 * Removed 'reset-cells' from cpg because resets not supported (yet?)
 * Sorted nodes by address (per group of device
---
 arch/arm/boot/dts/r7s9210.dtsi | 204 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 204 insertions(+)
 create mode 100644 arch/arm/boot/dts/r7s9210.dtsi

Rob Herring (Arm) Dec. 18, 2018, 3:05 p.m. UTC | #1

On Mon, Dec 17, 2018 at 09:43:23AM -0500, Chris Brandt wrote:
> Basic support for the RZ/A2 (R7S9210) SoC.
> 
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> ---
> v2:
>  * Fixed cpg node name to match reg address
>  * Removed the clocks subnode
>  * SCIF register range 18 to 0x18
>  * Removed 'reset-cells' from cpg because resets not supported (yet?)
>  * Sorted nodes by address (per group of device
> ---
>  arch/arm/boot/dts/r7s9210.dtsi | 204 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 204 insertions(+)
>  create mode 100644 arch/arm/boot/dts/r7s9210.dtsi
> 
> diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
> new file mode 100644
> index 000000000000..2b589226895e
> --- /dev/null
> +++ b/arch/arm/boot/dts/r7s9210.dtsi
> @@ -0,0 +1,204 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the R7S9210 SoC
> + *
> + * Copyright (C) 2018 Renesas Electronics Corporation
> + *
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/r7s9210-cpg-mssr.h>
> +
> +/ {
> +	compatible = "renesas,r7s9210";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	bsid: chipid@fcfe8004 {

Put all the mmio peripherals under a simple-bus node or nodes.

> +		compatible = "renesas,bsid";
> +		reg = <0xfcfe8004 4>;
> +	};
> +
> +	/* External clocks */
> +	extal_clk: extal {
> +		#clock-cells = <0>;
> +		compatible = "fixed-clock";
> +		/* Value must be set by board */
> +		clock-frequency = <0>;
> +	};
> +
> +	rtc_x1_clk: rtc_x1 {
> +		#clock-cells = <0>;
> +		compatible = "fixed-clock";
> +		/* If clk present, value (32678) must be set by board */
> +		clock-frequency = <0>;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			reg = <0>;
> +			clock-frequency = <528000000>;
> +			next-level-cache = <&L2>;
> +		};
> +	};
> +
> +	L2: cache-controller@1f003000 {
> +		compatible = "arm,pl310-cache";
> +		reg = <0x1f003000 0x1000>;
> +		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +		arm,early-bresp-disable;
> +		arm,full-line-zero-disable;
> +		cache-unified;
> +		cache-level = <2>;
> +	};
> +
> +	gic: interrupt-controller@e8221000 {
> +		compatible = "arm,gic-400";

Kind of strange that a single core A9 uses an external GIC rather than 
the built-in one.

> +		#interrupt-cells = <3>;
> +		#address-cells = <0>;
> +		interrupt-controller;
> +		reg = <0xe8221000 0x1000>,
> +		      <0xe8222000 0x1000>;
> +	};
> +
> +	cpg: clock-controller@fcfe0010 {
> +		compatible = "renesas,r7s9210-cpg-mssr";
> +		reg = <0xfcfe0010 0x455>;
> +		clocks = <&extal_clk>;
> +		clock-names = "extal";
> +		#clock-cells = <2>;
> +		#power-domain-cells = <0>;
> +	};
> +
> +	wdt: watchdog@fcfe7000 {
> +		compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt";
> +		reg = <0xfcfe7000 0x26>;
> +		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cpg CPG_CORE R7S9210_CLK_P0>;
> +	};
> +
> +	pinctrl: pin-controller@fcffe000 {
> +		compatible = "renesas,r7s9210-pinctrl";
> +		reg = <0xfcffe000 0x1000>;
> +
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		gpio-ranges = <&pinctrl 0 0 176>;
> +	};
> +
> +	scif0: serial@e8007000 {
> +		compatible = "renesas,scif-r7s9210";
> +		reg = <0xe8007000 0x18>;
> +		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei";
> +		clocks = <&cpg CPG_MOD 47>;
> +		clock-names = "fck";
> +		power-domains = <&cpg>;
> +		status = "disabled";
> +	};
> +
> +	scif1: serial@e8007800 {
> +		compatible = "renesas,scif-r7s9210";
> +		reg = <0xe8007800 0x18>;
> +		interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei";
> +		clocks = <&cpg CPG_MOD 46>;
> +		clock-names = "fck";
> +		power-domains = <&cpg>;
> +		status = "disabled";
> +	};
> +
> +	scif2: serial@e8008000 {
> +		compatible = "renesas,scif-r7s9210";
> +		reg = <0xe8008000 0x18>;
> +		interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei";
> +		clocks = <&cpg CPG_MOD 45>;
> +		clock-names = "fck";
> +		power-domains = <&cpg>;
> +		status = "disabled";
> +	};
> +
> +	scif3: serial@e8008800 {
> +		compatible = "renesas,scif-r7s9210";
> +		reg = <0xe8008800 0x18>;
> +		interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei";
> +		clocks = <&cpg CPG_MOD 44>;
> +		clock-names = "fck";
> +		power-domains = <&cpg>;
> +		status = "disabled";
> +	};
> +
> +	scif4: serial@e8009000 {
> +		compatible = "renesas,scif-r7s9210";
> +		reg = <0xe8009000 0x18>;
> +		interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei";
> +		clocks = <&cpg CPG_MOD 43>;
> +		clock-names = "fck";
> +		power-domains = <&cpg>;
> +		status = "disabled";
> +	};
> +
> +	ostm0: timer@e803b000 {
> +		compatible = "renesas,r7s9210-ostm", "renesas,ostm";
> +		reg = <0xe803b000 0x30>;
> +		interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
> +		clocks = <&cpg CPG_MOD 36>;
> +		clock-names = "ostm0";
> +		power-domains = <&cpg>;
> +		status = "disabled";
> +	};
> +
> +	ostm1: timer@e803c000 {
> +		compatible = "renesas,r7s9210-ostm", "renesas,ostm";
> +		reg = <0xe803c000 0x30>;
> +		interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
> +		clocks = <&cpg CPG_MOD 35>;
> +		clock-names = "ostm1";
> +		power-domains = <&cpg>;
> +		status = "disabled";
> +	};
> +
> +	ostm2: timer@e803d000 {
> +		compatible = "renesas,r7s9210-ostm", "renesas,ostm";
> +		reg = <0xe803d000 0x30>;
> +		interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>;
> +		clocks = <&cpg CPG_MOD 34>;
> +		clock-names = "ostm2";
> +		power-domains = <&cpg>;
> +		status = "disabled";
> +	};
> +};
> -- 
> 2.16.1
>

Chris Brandt Dec. 18, 2018, 3:40 p.m. UTC | #2

On Tuesday, December 18, 2018 1, Rob Herring wrote:
> > +/ {
> > +	compatible = "renesas,r7s9210";
> > +	interrupt-parent = <&gic>;
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +
> > +	bsid: chipid@fcfe8004 {
> 
> Put all the mmio peripherals under a simple-bus node or nodes.

Just to be clear on what you mean, basically put all the peripherals 
under a 'soc' node like the other Renesas parts?

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;

		#address-cells = <2>;
		#size-cells = <2>;
		ranges;


Thanks,
Chris

Rob Herring (Arm) Dec. 18, 2018, 3:44 p.m. UTC | #3

On Tue, Dec 18, 2018 at 9:40 AM Chris Brandt <Chris.Brandt@renesas.com> wrote:
>
> On Tuesday, December 18, 2018 1, Rob Herring wrote:
> > > +/ {
> > > +   compatible = "renesas,r7s9210";
> > > +   interrupt-parent = <&gic>;
> > > +   #address-cells = <1>;
> > > +   #size-cells = <1>;
> > > +
> > > +   bsid: chipid@fcfe8004 {
> >
> > Put all the mmio peripherals under a simple-bus node or nodes.
>
> Just to be clear on what you mean, basically put all the peripherals
> under a 'soc' node like the other Renesas parts?

Yes.

>
>         soc {
>                 compatible = "simple-bus";
>                 interrupt-parent = <&gic>;
>
>                 #address-cells = <2>;
>                 #size-cells = <2>;
>                 ranges;
>
>
> Thanks,
> Chris
>

Rob Herring (Arm) Dec. 19, 2018, 2:05 p.m. UTC | #4

On Tue, Dec 18, 2018 at 9:05 AM Rob Herring <robh@kernel.org> wrote:
>
> On Mon, Dec 17, 2018 at 09:43:23AM -0500, Chris Brandt wrote:
> > Basic support for the RZ/A2 (R7S9210) SoC.
> >
> > Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> > ---

> > +     gic: interrupt-controller@e8221000 {
> > +             compatible = "arm,gic-400";
>
> Kind of strange that a single core A9 uses an external GIC rather than
> the built-in one.

Still have this question on v4. It should be "arm,cortex-a9-gic" if
the A9 built-in GIC is used.

Rob

Geert Uytterhoeven Dec. 19, 2018, 2:22 p.m. UTC | #5

Hi Rob,

On Wed, Dec 19, 2018 at 3:07 PM Rob Herring <robh@kernel.org> wrote:
> On Tue, Dec 18, 2018 at 9:05 AM Rob Herring <robh@kernel.org> wrote:
> > On Mon, Dec 17, 2018 at 09:43:23AM -0500, Chris Brandt wrote:
> > > Basic support for the RZ/A2 (R7S9210) SoC.
> > >
> > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> > > ---
>
> > > +     gic: interrupt-controller@e8221000 {
> > > +             compatible = "arm,gic-400";
> >
> > Kind of strange that a single core A9 uses an external GIC rather than
> > the built-in one.
>
> Still have this question on v4. It should be "arm,cortex-a9-gic" if
> the A9 built-in GIC is used.

The GIC in RZ/A2 is documented to be a GIC-400.  Apparently the A9 GIC does
not have enough interrupt sources to serve all RZ/A2 peripherals.

Note that several Renesas A9 SoCs use a PL390.

https://lore.kernel.org/lkml/20150429125703.GB11757@leverpostej/
has a patch to print the GIC variant ID at runtime, to be 100% sure.

0x0000043b = arm,pl390
0x0102043b = arm,cortex-a9-gic
0x0200043b = arm,gic-400

Gr{oetje,eeting}s,

                        Geert

[v3,1/2] ARM: dts: r7s9210: Initial SoC device tree

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