| Message ID | 20181218091232.23532-3-josephl@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Tegra210 DFLL support | expand |
On Tue, 18 Dec 2018 17:12:14 +0800, Joseph Lo wrote: > Add Tegra210 support for DFLL clock. > > Cc: devicetree@vger.kernel.org > Signed-off-by: Joseph Lo <josephl@nvidia.com> > Acked-by: Jon Hunter <jonathanh@nvidia.com> > --- > *V3: > - no change > *V2: > - add ack tag > --- > .../devicetree/bindings/clock/nvidia,tegra124-dfll.txt | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > Reviewed-by: Rob Herring <robh@kernel.org>
Quoting Joseph Lo (2018-12-18 01:12:14) > Add Tegra210 support for DFLL clock. > > Cc: devicetree@vger.kernel.org > Signed-off-by: Joseph Lo <josephl@nvidia.com> > Acked-by: Jon Hunter <jonathanh@nvidia.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org>
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt index 38e8cc8c70a8..8a38c8e78acf 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt @@ -10,7 +10,9 @@ control module that will automatically adjust the VDD_CPU voltage by communicating with an off-chip PMIC either via an I2C bus or via PWM signals. Required properties: -- compatible : should be "nvidia,tegra124-dfll" +- compatible : should be one of: + - "nvidia,tegra124-dfll": for Tegra124 + - "nvidia,tegra210-dfll": for Tegra210 - reg : Defines the following set of registers, in the order listed: - registers for the DFLL control logic. - registers for the I2C output logic.