| Message ID | 20181220173026.3857-3-jcrouse@codeaurora.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | arm64: dts: sdm845: Add sdm845 GPU interconnect | expand |
Hi, On Thu, Dec 20, 2018 at 9:30 AM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > Add documentation for the interconnect and interconnect-names bindings > for the GPU node as detailed by bindings/interconnect/interconnect.txt. > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > --- > > Documentation/devicetree/bindings/display/msm/gpu.txt | 4 ++++ > 1 file changed, 4 insertions(+) I would have been fine if you had kept my tag (even though 50% of the patch changed!). ...but here it is again: Reviewed-by: Douglas Anderson <dianders@chromium.org> I assume this will be going through Georgi's tree w/ the previous patch. -Doug
On Thu, 20 Dec 2018 10:30:25 -0700, Jordan Crouse wrote: > Add documentation for the interconnect and interconnect-names bindings > for the GPU node as detailed by bindings/interconnect/interconnect.txt. > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > --- > > Documentation/devicetree/bindings/display/msm/gpu.txt | 4 ++++ > 1 file changed, 4 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
Hi, On 12/20/18 19:30, Jordan Crouse wrote: > Add documentation for the interconnect and interconnect-names bindings > for the GPU node as detailed by bindings/interconnect/interconnect.txt. > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > --- > > Documentation/devicetree/bindings/display/msm/gpu.txt | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt > index 9c89f4fdb8ca..5b04393dcb15 100644 > --- a/Documentation/devicetree/bindings/display/msm/gpu.txt > +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt > @@ -20,6 +20,8 @@ Required properties: > - qcom,adreno-630.2 > - iommus: optional phandle to an adreno iommu instance > - operating-points-v2: optional phandle to the OPP operating points > +- interconnect: optional phandle to a interconnect provider. See Nit: s/interconnect:/interconnects:/ Nit: s/a interconnect/an interconnect/ > + ../interconnect/interconnect.txt for details. > - qcom,gmu: For GMU attached devices a phandle to the GMU device that will > control the power for the GPU. Applicable targets: > - qcom,adreno-630.2 > @@ -68,6 +70,8 @@ Example a6xx (with GMU): > > operating-points-v2 = <&gpu_opp_table>; > > + interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; > + > qcom,gmu = <&gmu>; > }; > }; > Acked-by: Georgi Djakov <georgi.djakov@linaro.org> Thanks, Georgi
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 9c89f4fdb8ca..5b04393dcb15 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -20,6 +20,8 @@ Required properties: - qcom,adreno-630.2 - iommus: optional phandle to an adreno iommu instance - operating-points-v2: optional phandle to the OPP operating points +- interconnect: optional phandle to a interconnect provider. See + ../interconnect/interconnect.txt for details. - qcom,gmu: For GMU attached devices a phandle to the GMU device that will control the power for the GPU. Applicable targets: - qcom,adreno-630.2 @@ -68,6 +70,8 @@ Example a6xx (with GMU): operating-points-v2 = <&gpu_opp_table>; + interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; + qcom,gmu = <&gmu>; }; };
Add documentation for the interconnect and interconnect-names bindings for the GPU node as detailed by bindings/interconnect/interconnect.txt. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> --- Documentation/devicetree/bindings/display/msm/gpu.txt | 4 ++++ 1 file changed, 4 insertions(+)