| Message ID | 20190117042940.25487-3-bjorn.andersson@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: qcom: sdm845: Fix DMA allocations for devices with IOMMU | expand |
Hi, On Wed, Jan 16, 2019 at 8:30 PM Bjorn Andersson <bjorn.andersson@linaro.org> wrote: > > For devices attached to an IOMMU, translation between IOVA and physical > addresses is no longer 1:1 and dma-ranges should be specified to > describe the available IOVA address space. > > On SDM845 the busses are implemented with 36 address bits, so dma-ranges > must be defined to reduce the size of the IOVA address space from the 48 > bits supported by the SMMU. Without this DMA allocations may end up with > IOVAs outside the valid range, that gets truncated by the bus between > the device and its translation unit. > > Also extend ranges to describe the available address space. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > > Changes since v3: > - Split this out from patch 1. > - Rewrote commit message from scratch > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org>
Quoting Bjorn Andersson (2019-01-16 20:29:40) > For devices attached to an IOMMU, translation between IOVA and physical > addresses is no longer 1:1 and dma-ranges should be specified to > describe the available IOVA address space. > > On SDM845 the busses are implemented with 36 address bits, so dma-ranges > must be defined to reduce the size of the IOVA address space from the 48 > bits supported by the SMMU. Without this DMA allocations may end up with > IOVAs outside the valid range, that gets truncated by the bus between > the device and its translation unit. > > Also extend ranges to describe the available address space. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 9867d42dc836..143c5af32e7b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -353,7 +353,8 @@ soc: soc { #address-cells = <2>; #size-cells = <2>; - ranges = <0 0 0 0 0 0xffffffff>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; compatible = "simple-bus"; gcc: clock-controller@100000 {
For devices attached to an IOMMU, translation between IOVA and physical addresses is no longer 1:1 and dma-ranges should be specified to describe the available IOVA address space. On SDM845 the busses are implemented with 36 address bits, so dma-ranges must be defined to reduce the size of the IOVA address space from the 48 bits supported by the SMMU. Without this DMA allocations may end up with IOVAs outside the valid range, that gets truncated by the bus between the device and its translation unit. Also extend ranges to describe the available address space. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- Changes since v3: - Split this out from patch 1. - Rewrote commit message from scratch arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)