| Message ID | 20190117044006.12463-1-bjorn.andersson@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: qcom: sdm845-mtp: Add WCN3990 BT node | expand |
Hi Anderson, On 2019-01-17 10:10, Bjorn Andersson wrote: > The SDM845 MTP has a WCN3990 Bluetooth chip on UART6, enable this. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 44 +++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > index af8c6a2445a2..f65d5a674103 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > @@ -17,6 +17,7 @@ > > aliases { > serial0 = &uart9; > + hsuart0 = &uart6; > }; > > chosen { > @@ -357,6 +358,10 @@ > clock-frequency = <400000>; > }; > > +&qupv3_id_0 { > + status = "okay"; > +}; > + > &qupv3_id_1 { > status = "okay"; > }; > @@ -373,6 +378,20 @@ > cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; > }; > > +&uart6 { > + status = "okay"; > + > + bluetooth { > + compatible = "qcom,wcn3990-bt"; > + > + vddio-supply = <&vreg_s4a_1p8>; > + vddxo-supply = <&vreg_l7a_1p8>; > + vddrf-supply = <&vreg_l17a_1p3>; > + vddch0-supply = <&vreg_l25a_3p3>; > + max-speed = <3200000>; > + }; > +}; > + > &uart9 { > status = "okay"; > }; > @@ -470,6 +489,31 @@ > }; > }; > > +&qup_uart6_default { > + pinmux { > + pins = "gpio45", "gpio46", "gpio47", "gpio48"; > + function = "qup6"; > + }; > + > + ctsrx { > + pins = "gpio45", "gpio48"; > + drive-strength = <2>; > + bias-no-pull; > + }; > + > + rts { > + pins = "gpio46"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + tx { > + pins = "gpio47"; > + drive-strength = <2>; > + bias-pull-up; > + }; > +}; > + > &qup_uart9_default { > pinconf-tx { > pins = "gpio4"; [Bala]: GPIO 45 is CTS GPIO 46 is RTS GPIO 47 is Tx GPIO 48 is Rx. Tx & RTS are inputs to APPS processor, bias should be disable as the source i.e. BT chip will pull them up. CTS & RX are outputs from APPS processor, where as CTS is GPIO which need to toggled, so the default state should be pull down. RX is should be pulled up. when TX & RX are pulled high it indicates that the lines are ideal i.e. no data. Above is just my assumption, not sure whether they work on MTP.
On Wed, Jan 16, 2019 at 08:40:06PM -0800, Bjorn Andersson wrote: > The SDM845 MTP has a WCN3990 Bluetooth chip on UART6, enable this. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 44 +++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > index af8c6a2445a2..f65d5a674103 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > @@ -17,6 +17,7 @@ > > aliases { > serial0 = &uart9; > + hsuart0 = &uart6; > }; > > chosen { > @@ -357,6 +358,10 @@ > clock-frequency = <400000>; > }; > > +&qupv3_id_0 { > + status = "okay"; > +}; > + > &qupv3_id_1 { > status = "okay"; > }; > @@ -373,6 +378,20 @@ > cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; > }; > > +&uart6 { > + status = "okay"; > + > + bluetooth { > + compatible = "qcom,wcn3990-bt"; > + > + vddio-supply = <&vreg_s4a_1p8>; > + vddxo-supply = <&vreg_l7a_1p8>; > + vddrf-supply = <&vreg_l17a_1p3>; > + vddch0-supply = <&vreg_l25a_3p3>; > + max-speed = <3200000>; > + }; > +}; > + > &uart9 { > status = "okay"; > }; > @@ -470,6 +489,31 @@ > }; > }; > > +&qup_uart6_default { > + pinmux { > + pins = "gpio45", "gpio46", "gpio47", "gpio48"; > + function = "qup6"; > + }; > + > + ctsrx { > + pins = "gpio45", "gpio48"; > + drive-strength = <2>; CTS and RX are input signals, no need to configure drive strength in this case IIUC. > + bias-no-pull; On another SDM845 based device we observe garbage on RX at initialization time, unless we enable a pull-up. > + }; > + > + rts { > + pins = "gpio46"; > + drive-strength = <2>; > + bias-pull-down; > + }; On our device we don't configure a pull on the lines driven by the AP. I think a pull-down on RTS should be fine though since it matches the pull (during reset) on CTS of the BT module. > + tx { > + pins = "gpio47"; > + drive-strength = <2>; > + bias-pull-up; > + }; > +}; Similar to RTS, the pull matches the one on RXD of the BT module. For reference, this is what we currently use on our device: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/1391888/3/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi Cheers Matthias
On Wed 16 Jan 22:10 PST 2019, Balakrishna Godavarthi wrote: > Hi Anderson, > > On 2019-01-17 10:10, Bjorn Andersson wrote: [..] > > +&qup_uart6_default { > > + pinmux { > > + pins = "gpio45", "gpio46", "gpio47", "gpio48"; > > + function = "qup6"; > > + }; > > + > > + ctsrx { > > + pins = "gpio45", "gpio48"; > > + drive-strength = <2>; > > + bias-no-pull; > > + }; > > + > > + rts { > > + pins = "gpio46"; > > + drive-strength = <2>; > > + bias-pull-down; > > + }; > > + > > + tx { > > + pins = "gpio47"; > > + drive-strength = <2>; > > + bias-pull-up; > > + }; > > +}; > > + > > &qup_uart9_default { > > pinconf-tx { > > pins = "gpio4"; > > > [Bala]: > GPIO 45 is CTS > GPIO 46 is RTS > GPIO 47 is Tx > GPIO 48 is Rx. > > Tx & RTS are inputs to APPS processor, bias should be disable as the > source i.e. BT chip will pull them up. > CTS & RX are outputs from APPS processor, where as CTS is GPIO which > need to toggled, so the default state should be pull down. > RX is should be pulled up. > when TX & RX are pulled high it indicates that the lines are ideal > i.e. no data. > > Above is just my assumption, not sure whether they work on MTP. > I will update and verify. Thanks, Bjorn
On Thu 17 Jan 11:28 PST 2019, Matthias Kaehlcke wrote: > On Wed, Jan 16, 2019 at 08:40:06PM -0800, Bjorn Andersson wrote: [..] > > +&qup_uart6_default { > > + pinmux { > > + pins = "gpio45", "gpio46", "gpio47", "gpio48"; > > + function = "qup6"; > > + }; > > + > > + ctsrx { > > + pins = "gpio45", "gpio48"; > > + drive-strength = <2>; > > CTS and RX are input signals, no need to configure drive strength in > this case IIUC. > Right, didn't think that far when I hacked this up. > > + bias-no-pull; > > On another SDM845 based device we observe garbage on RX at > initialization time, unless we enable a pull-up. > > > + }; > > + > > + rts { > > + pins = "gpio46"; > > + drive-strength = <2>; > > + bias-pull-down; > > + }; > > On our device we don't configure a pull on the lines driven by the > AP. I think a pull-down on RTS should be fine though since it matches > the pull (during reset) on CTS of the BT module. > > > + tx { > > + pins = "gpio47"; > > + drive-strength = <2>; > > + bias-pull-up; > > + }; > > +}; > > Similar to RTS, the pull matches the one on RXD of the BT module. > > For reference, this is what we currently use on our device: > > https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/1391888/3/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi > Thanks, I will update the patch. Regards, Bjorn
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index af8c6a2445a2..f65d5a674103 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -17,6 +17,7 @@ aliases { serial0 = &uart9; + hsuart0 = &uart6; }; chosen { @@ -357,6 +358,10 @@ clock-frequency = <400000>; }; +&qupv3_id_0 { + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; @@ -373,6 +378,20 @@ cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; }; +&uart6 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + }; +}; + &uart9 { status = "okay"; }; @@ -470,6 +489,31 @@ }; }; +&qup_uart6_default { + pinmux { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "qup6"; + }; + + ctsrx { + pins = "gpio45", "gpio48"; + drive-strength = <2>; + bias-no-pull; + }; + + rts { + pins = "gpio46"; + drive-strength = <2>; + bias-pull-down; + }; + + tx { + pins = "gpio47"; + drive-strength = <2>; + bias-pull-up; + }; +}; + &qup_uart9_default { pinconf-tx { pins = "gpio4";
The SDM845 MTP has a WCN3990 Bluetooth chip on UART6, enable this. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 44 +++++++++++++++++++++++++ 1 file changed, 44 insertions(+)