diff mbox series

MIPS: Compile post DMA flush only when needed

Message ID 20181209154957.28403-1-hauke@hauke-m.de (mailing list archive)
State Mainlined
Commit f263f2a2c682fddc7521a1d1efc01d58e1d70d84
Headers show
Series MIPS: Compile post DMA flush only when needed | expand

Commit Message

Hauke Mehrtens Dec. 9, 2018, 3:49 p.m. UTC
dma_sync_phys() is only called for some CPUs when a mapping is removed.
Add ARCH_HAS_SYNC_DMA_FOR_CPU only for the CPUs listed in
cpu_needs_post_dma_flush() which need this extra call and do not compile
this code in for other CPUs. We need this for R10000, R12000, BMIPS5000
CPUs and CPUs supporting MAAR which was introduced in MIPS32r5.

This will hopefully improve the performance of the not affected devices.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 arch/mips/Kconfig              | 6 +++++-
 arch/mips/mm/dma-noncoherent.c | 2 ++
 2 files changed, 7 insertions(+), 1 deletion(-)

Comments

Paul Burton Jan. 18, 2019, 7:33 p.m. UTC | #1
Hello,

Hauke Mehrtens wrote:
> dma_sync_phys() is only called for some CPUs when a mapping is removed.
> Add ARCH_HAS_SYNC_DMA_FOR_CPU only for the CPUs listed in
> cpu_needs_post_dma_flush() which need this extra call and do not compile
> this code in for other CPUs. We need this for R10000, R12000, BMIPS5000
> CPUs and CPUs supporting MAAR which was introduced in MIPS32r5.
> 
> This will hopefully improve the performance of the not affected devices.
> 
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

Applied to mips-next.

Thanks,
    Paul

[ This message was auto-generated; if you believe anything is incorrect
  then please email paul.burton@mips.com to report it. ]
diff mbox series

Patch

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 653f52f2f383..c0708fdd7933 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1119,7 +1119,6 @@  config DMA_NONCOHERENT
 	bool
 	select ARCH_HAS_DMA_MMAP_PGPROT
 	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
-	select ARCH_HAS_SYNC_DMA_FOR_CPU
 	select NEED_DMA_MAP_STATE
 	select ARCH_HAS_DMA_COHERENT_TO_PFN
 	select DMA_NONCOHERENT_CACHE_SYNC
@@ -1923,9 +1922,11 @@  config SYS_HAS_CPU_MIPS32_R3_5
 
 config SYS_HAS_CPU_MIPS32_R5
 	bool
+	select ARCH_HAS_SYNC_DMA_FOR_CPU
 
 config SYS_HAS_CPU_MIPS32_R6
 	bool
+	select ARCH_HAS_SYNC_DMA_FOR_CPU
 
 config SYS_HAS_CPU_MIPS64_R1
 	bool
@@ -1935,6 +1936,7 @@  config SYS_HAS_CPU_MIPS64_R2
 
 config SYS_HAS_CPU_MIPS64_R6
 	bool
+	select ARCH_HAS_SYNC_DMA_FOR_CPU
 
 config SYS_HAS_CPU_R3000
 	bool
@@ -1971,6 +1973,7 @@  config SYS_HAS_CPU_R8000
 
 config SYS_HAS_CPU_R10000
 	bool
+	select ARCH_HAS_SYNC_DMA_FOR_CPU
 
 config SYS_HAS_CPU_RM7000
 	bool
@@ -1999,6 +2002,7 @@  config SYS_HAS_CPU_BMIPS4380
 config SYS_HAS_CPU_BMIPS5000
 	bool
 	select SYS_HAS_CPU_BMIPS
+	select ARCH_HAS_SYNC_DMA_FOR_CPU
 
 config SYS_HAS_CPU_XLR
 	bool
diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
index cb38461391cb..f7e0fd6b7619 100644
--- a/arch/mips/mm/dma-noncoherent.c
+++ b/arch/mips/mm/dma-noncoherent.c
@@ -145,12 +145,14 @@  void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr,
 	dma_sync_phys(paddr, size, dir);
 }
 
+#ifdef CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU
 void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr,
 		size_t size, enum dma_data_direction dir)
 {
 	if (cpu_needs_post_dma_flush(dev))
 		dma_sync_phys(paddr, size, dir);
 }
+#endif
 
 void arch_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
 		enum dma_data_direction direction)